Memory device and test method thereof

Patent metadata

Field	Value
Publication number	US-10658064-B2
Application number	US-201715794142-A
Country	US
Kind code	B2
Filing date	Oct 26, 2017
Priority date	Mar 17, 2017
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A test method for a memory device which includes performing a first write operation of writing test data to first regions of a normal cell region and a parity cell region, and storing a parity bit generated based on the test data in a temporary storage circuit, performing a second write operation of writing the parity bit stored in the temporary storage circuit to a second region of the parity cell region, performing a first read operation of reading the parity bit from the second region of the parity cell region, and storing the parity bit into the temporary storage circuit, and performing a second read operation of reading the test data from the first regions of the normal cell region and the parity cell region, correcting an error of the test data using the parity bit stored in the temporary storage circuit, and outputting error-corrected test data.

First claim

What is claimed is:

1. A test method for a memory device, comprising:
performing a first write operation of writing test data provided from an external device to first regions of a normal cell region and a parity cell region, and storing parity bits generated based on the test data in a temporary storage circuit;
performing a second write operation of writing the parity bits stored in the temporary storage circuit to a second region of the parity cell region, wherein the parity cell region stores both of the test data and the parity bits after the second write operation;
performing a first read operation of reading the parity bits from the second region of the parity cell region, and storing the parity bits into the temporary storage circuit; and
performing a second read operation of reading the test data from the first regions of the normal cell region and the parity cell region, correcting an error of the test data using the parity bits stored in the temporary storage circuit, and outputting error-corrected test data.

2. The test method of claim 1 , further comprising:
receiving a write command and an external address; and
generating a first internal address based on the external address,
wherein the first write operation is performed according to the write command and the first internal address.

3. The test method of claim 2 , further comprising:
generating an internal write command which is activated at a predetermined time after the write command is inputted; and
generating a second internal address by toggling a most significant bit (MSB) of the first internal address in response to the internal write command,
wherein the second write operation is performed according to the internal write command and the second internal address.

4. The test method of claim 3 , wherein the predetermined time is set to ½*tCCD (column address strobe (CAS) to CAS Command Delay).

5. The test method of claim 2 , further comprising:
receiving a read command and the external address; and
generating a third internal address by toggling a most significant bit (MSB) of the external address,
wherein the first read operation is performed according to the read command and the third internal address.

6. The test method of claim 5 , further comprising:
generating an internal read command which is activated at a predetermined time after the read command is inputted; and
generating a fourth internal address by toggling an MSB of the third internal address,
wherein the second read operation is performed according to the internal read command and the fourth internal address.

7. The test method of claim 6 , wherein the predetermined time is set to ½*tCCD.

8. The test method of claim 1 , wherein, during the second write operation, garbage data are written to a second region of the normal cell region.

9. The test method of claim 1 , after the second read operation, further comprising:
comparing the error-corrected test data with a preset test pattern and outputting a comparison result.

10. A memory device comprising:
a normal cell region and a parity cell region;
a parity storage circuit suitable for temporarily storing write parity bits and read parity bits;
a write circuit suitable for writing test data provided from an external device to first regions of the normal cell region and the parity cell region, and writing the write parity bits stored in the parity storage circuit to a second region of the parity cell region, wherein the parity cell region stores both of the test data and the parity bits after writing;
a read circuit suitable for reading parity bits from the second region of the parity cell region to provide the read parity bits to the parity storage circuit, and reading the test data from the first regions of the normal cell region and the parity cell region; and
an error correction circuit suitable for correcting an error of the test data read from the first regions of the normal cell region and the parity cell region, using the read parity bits stored in the parity storage circuit.

11. The memory device of claim 10 , further comprising:
an additional command generator circuit suitable for generating an internal write command which is activated at a predetermined time after a write command is inputted; and
an internal address generator circuit suitable for generating a first internal address using an external address in response to the write command, and generating a second internal address by toggling a most significant bit (MSB) of the first internal address in response to the internal write command.

12. The memory device of claim 11 , wherein the write circuit writes the test data to the first regions of the normal cell region and the parity cell region, which correspond to the first internal address in response to the write command, and writes the write parity bits to the second region of the parity cell region, which corresponds to the second internal address in response to the internal write command.

13. The memory device of claim 10 , further comprising:
an additional command generator circuit suitable for generating an internal read command which is activated at a predetermined time after a read command is inputted; and
an internal address generator circuit suitable for generating a third internal address by toggling a most significant bit (MSB) of an external address in response to the read command, and generating a fourth internal address by toggling an MSB of the third internal address in response to the internal read command.

14. The memory device of claim 13 , wherein the read circuit reads the read parity bits from the second region of the parity cell region, which corresponds to the third internal address in response to the read command, and reads the test data from the first regions of the normal cell region and the parity cell region, which correspond to the fourth internal address in response to the internal read command.

15. The memory device of claim 10 , further comprising:
a test output circuit suitable for comparing error-corrected test data outputted from the error correction circuit with a preset test pattern, and outputting a comparison result.

16. A memory device comprising:
a normal cell region and a parity cell region;
an additional command generator circuit suitable for generating an internal read command or an internal write command which is activated at a predetermined time after a read command or a write command is inputted;
a parity generation circuit suitable for generating parity bits for test data provided from an external device in response to the write command;
a parity storage circuit suitable for storing the parity bits in response to the read command or the write command, and outputting the stored parity bits in response to the internal read command or the internal write command;
a write circuit suitable for writing the test data to first regions of the normal cell region and the parity cell region according to the write command, and writing the parity bits stored in the parity storage circuit to a second region of the parity cell region according to the internal write command, wherein the parity cell region stores both of the test data and the parity bits after writing;
a read circuit suitable for reading the parity bits from the second region of the parity cell region according to the read command, and reading the test data from the first regions of the normal cell region and the parity cell region according to the internal read command; and
an error correction circuit suitable for correcting an error of the test data read from

Assignees

• Sk Hynix Inc

Inventors

• Lee Jeong-Jun

Classifications

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title

• G11C29/36

  Data generation devices, e.g. data inverters · CPC title

• G11C29/30

  Accessing single arrays · CPC title

• G11C29/24

  Accessing extra cells, e.g. dummy cells or redundant cells · CPC title

• G11C29/18

  Address generation devices; Devices for accessing memories, e.g. details of addressing circuits · CPC title