Nonvolatile semiconductor memory including a read operation

Patent metadata

Field	Value
Publication number	US-10658039-B2
Application number	US-201816149862-A
Country	US
Kind code	B2
Filing date	Oct 2, 2018
Priority date	Dec 3, 2008
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

First claim

What is claimed is:

1. A memory device comprising:
a first transistor;
a second transistor;
a plurality of memory cells electrically connected in series between the first transistor and the second transistor;
a source line electrically connected to the first transistor;
a bit line electrically connected to the second transistor;
a plurality of word lines electrically connected to gates of the memory cells, respectively;
a sense amplifier including
a first node,
a third transistor having a first end electrically connected to the bit line and a second end electrically connected to the first node,
a fourth transistor having a first end electrically connected to the second end of the third transistor and to the first node,
a fifth transistor having a gate electrically connected to the first node,
a sixth transistor having a first end electrically connected to a first end of the fifth transistor,
a seventh transistor having a first end electrically connected to the first end of the fifth transistor,
a first data latch electrically connected to a second end of the sixth transistor, and
a second data latch electrically connected to a second end of the seventh transistor, and

a controller configured to perform a read operation including a first period, a second period after the first period, a third period after the second period, and a fourth period after the third period, and
at least during the first to third periods, a first voltage being applied to one of the word lines, and a second voltage higher than the first voltage being applied to another one of the word lines,
during the first period, a third voltage being applied to a gate of the fourth transistor, and a fourth voltage higher than the third voltage being applied to a gate of the third transistor,
during the second period, a fifth voltage being applied to a gate of the sixth transistor to thereby turn on the sixth transistor,
during the third period, a sixth voltage being applied to the gate of the fourth transistor, and a seventh voltage higher than the sixth voltage being applied to the gate of the third transistor,
during the fourth period, an eighth voltage being applied to a gate of the seventh transistor to thereby turn on the seventh transistor.

2. The memory device according to claim 1 ,
wherein the sense amplifier further includes a first capacitor having a first end connected to the first node.

3. The memory device according to claim 1 ,
wherein during the first to fourth periods, the first voltage is applied to the one of the word lines, and the second voltage is applied to the another one of the word lines.

4. The memory device according to claim 1 ,
wherein at least during the first to third periods, a voltage applied to the bit line is kept at a same level.

5. The memory device according to claim 4 ,
wherein at least during the first to third periods, the voltage applied to the bit line is kept at the same level regardless of data stored in the memory cell corresponding to the one of the word lines.

6. The memory device according to claim 1 , further comprising an eighth transistor having one end electrically connected to one end of the fifth transistor and having a gate which receives a control signal, wherein
the control signal is activated during both the second period and the fourth period.

7. A method of controlling a memory device, the memory device including a first transistor, a second transistor, a plurality of memory cells, a source line, a bit line, a plurality of word lines, and a sense amplifier, the sense amplifier including:
a first node,
a third transistor having a first end electrically connected to the bit line and a second end electrically connected to the first node,
a fourth transistor having a first end electrically connected to the second end of the third transistor and to the first node,
a fifth transistor having a gate electrically connected to the first node,
a sixth transistor having a first end electrically connected to a first end of the fifth transistor,
a seventh transistor having a first end electrically connected to the first end of the fifth transistor,
a first data latch electrically connected to a second end of the sixth transistor, and
a second data latch electrically connected to a second end of the seventh transistor,
the method comprising:
applying a first voltage to a first one of the word lines and a second voltage higher than the first voltage to a second one of the word lines during a first period, a second period after the first period, and a third period after the second period;
applying a third voltage to a gate of the fourth transistor and a fourth voltage higher than the third voltage to a gate of the third transistor during the first period,
applying a fifth voltage to a gate of the sixth transistor to thereby turn on the sixth transistor during the second period,
applying a sixth voltage to the gate of the fourth transistor and a seventh voltage higher than the sixth voltage to the gate of the third transistor during the third period, and
applying an eighth voltage to a gate of the seventh transistor to thereby turn on the seventh transistor during a fourth period after the third period.

8. The method according to claim 7 , further comprising applying the first voltage to the first one of the word lines and the second voltage to the second one of the word lines during the fourth period.

9. The method according to claim 7 , further comprising applying a voltage of a same level to the bit line during the first to third periods.

10. The method according to claim 9 , the applying of a voltage of the same level includes applying the voltage of the same level to the bit line during the first to third periods regardless of data stored in the memory cell corresponding to the first one of the word lines.

11. The method according to claim 7 ,
wherein the memory device further comprises an eighth transistor having one end electrically connected to one end of the fifth transistor and having a gate which receives a control signal, and
the method further comprises activating the control signal during both the second period and the fourth period.

Assignees

• Toshiba Memory Corp

Inventors

• Iwai Makoto
• Nakamura Hiroshi

Classifications

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/06

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C11/5642 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title