Semiconductor memory device having memory cell pairs defining data based on threshold voltages

Patent metadata

Field	Value
Publication number	US-10658031-B2
Application number	US-201816112655-A
Country	US
Kind code	B2
Filing date	Aug 25, 2018
Priority date	Nov 9, 2017
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

To provide a semiconductor memory device capable of storing multi-value data while suppressing an increase in the threshold voltage set for a memory cell. A semiconductor memory device according to an embodiment includes a plurality of memory cell pairs, each having a first memory cell and a second memory cell. The first memory cell is configured so as to set at least one threshold voltage, whereas the second memory cell is configured so as to set a plurality of threshold voltages. Data stored in the memory cell pairs is defined using differences between the threshold voltages of the second memory cell and the threshold voltage of the first memory cell.

First claim

What is claimed is:

1. A semiconductor memory device comprising a plurality of memory cells,
wherein the memory cells have a plurality of memory cell pairs, each having a first memory cell and a second memory cell,
wherein the first memory cell is configured so as to set a first threshold voltage,
wherein the second memory cell is configured so as to set second to fourth threshold voltages, and
wherein data stored in the memory cell pairs is defined using a difference between the second threshold voltage and the first threshold voltage, a difference between the third threshold voltage and the first threshold voltage, and a difference between the fourth threshold voltage and the first threshold voltage.

2. The semiconductor memory device according to claim 1 ,
wherein the first to fourth threshold voltages are set so as to increase in an order of the first threshold voltage, the second threshold voltage, the third threshold voltage, and the fourth threshold voltage, and
wherein voltage differences are set so as to increase in an order of the difference between the second threshold voltage and the first threshold voltage, the difference between the third threshold voltage and the second threshold voltage, and the difference between the fourth threshold voltage and the third threshold voltage.

3. The semiconductor memory device according to claim 1 ,
wherein the threshold voltages of the first and second memory cells are both positive or negative values.

4. The semiconductor memory device according to claim 1 ,
wherein the threshold voltage of one of the first and second memory cells is a positive value and the threshold voltage of the other memory cell is a negative value.

5. A semiconductor memory device comprising a plurality of memory cells,
wherein the memory cells have a plurality of memory cell pairs, each having a first memory cell and a second memory cell,
wherein the first memory cell is configured so as to set at least one threshold voltage,
wherein the second memory cell is configured so as to set a plurality of threshold voltages, and
wherein data stored in the memory cell pairs is defined using differences between the threshold voltages of the second memory cell and the threshold voltage of the first memory cell,
wherein the semiconductor memory device further comprises:
a threshold voltage detecting unit that detects the threshold voltages of the memory cells;
a memory controller that controls the memory cells; and
a timer that measures an elapsed time from a time of data writing in the first and second memory cells,
wherein the memory controller reads the data stored in the memory cell pairs, by using differences between the threshold voltages of the second memory cell and the threshold voltage of the first memory cell and the elapsed times measured by the timer, the threshold voltages being detected by the threshold voltage detecting unit.

Assignees

• Renesas Electronics Corp

Inventors

• Nagase Hirokazu

Classifications

• G11C16/32

  Timing circuits · CPC title

• G11C11/5642 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title

• G11C2211/5644

  Multilevel memory comprising counting devices · CPC title

• G11C2211/5641

  Multilevel memory having cells with different number of storage levels · CPC title