Texture value patch used in GPU-executed program sequence cross-compilation

Patent metadata

Field	Value
Publication number	US-10657698-B2
Application number	US-201815862870-A
Country	US
Kind code	B2
Filing date	Jan 5, 2018
Priority date	Jun 22, 2017
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A computing system configured to execute instructions for a first graphical processing unit (GPU) on a second GPU is provided. The computing system may include the second GPU and a processor. The processor may be configured to receive second GPU state data that indicates one or more global properties of the second GPU. The processor may be further configured to receive one or more binary instructions for texture operation configured to be executed on the first GPU. Based on the second GPU state data, the processor may be further configured to apply a texture value patch to the one or more binary instructions. Applying the texture value patch may translate the one or more binary instructions into one or more translated binary instructions configured to be executed on the second GPU.

First claim

The invention claimed is:

1. A computing system configured to execute instructions for a first graphical processing unit (GPU) on a second GPU, the computing system comprising:
the second GPU; and
a processor configured to:
receive second GPU state data that indicates one or more global properties of the second GPU;
receive one or more binary instructions for texture operations configured for the first GPU, wherein:
the one or more binary instructions include one or more texture fetches, and
each texture fetch includes a texture fetch constant having a respective sign for each of one or more channels that encode coordinates for the texture fetch;

determine a texture value patch type based at least in part on the one or more signs included in the one or more binary instructions, wherein the texture value patch type is incompatible signs, gamma, depth, or bias; and
based on the second GPU state data, apply a texture value patch of the texture value patch type to the one or more binary instructions, wherein applying the texture value patch translates the one or more binary instructions into one or more translated binary instructions configured to be executed on the second GPU.

2. The computing system of claim 1 , further comprising a display, wherein
each texture fetch of the one or more texture fetches returns a texture value to be displayed on the display.

3. The computing system of claim 2 , wherein each texture fetch of the one or more texture fetches is invoked by instructions that include as arguments a texture ID and the coordinates for the texture fetch.

4. The computing system of claim 2 , wherein the texture value patch is an incompatible signs texture value patch configured to translate a texture fetch into a plurality of translated texture fetches.

5. The computing system of claim 2 , wherein the texture value patch is a gamma patch configured to convert fetched texture values that are gamma encoded according to a first gamma correction curve of the first GPU and processed in hardware by the second GPU as if they were encoded according to the second gamma correction curve to corrected texture values that are linear or near linear encoded in a first linear encoding space of the first GPU.

6. The computing system of claim 5 , wherein the gamma patch converts the texture values at least in part using a lookup table.

7. The computing system of claim 2 , wherein the texture fetch constant further includes one or more of a data format, texture edge data, and channel order data.

8. The computing system of claim 1 , wherein the one or more global properties of the second GPU include an instruction set architecture (ISA) of the second GPU and/or an application binary interface (ABI) of the second GPU.

9. The computing system of claim 1 , wherein the processor is further configured to receive first GPU state data that indicates one or more global properties of the first GPU including an instruction set architecture (ISA) of the first GPU and/or an application binary interface (ABI) of the first GPU, and wherein the texture value patch is applied based at least in part on the one or more global properties of the first GPU.

10. A method for executing instructions for a first graphical processing unit (GPU) on a second GPU, the method comprising:
receiving second GPU state data that indicates one or more global properties of the second GPU;
receiving one or more binary instructions for texture operations configured for the first GPU, wherein:
the one or more binary instructions include one or more texture fetches, and
each texture fetch includes a texture fetch constant having a respective sign for each of one or more channels that encode coordinates for the texture fetch;

determining a texture value patch type based at least in part on the one or more signs included in the one or more binary instructions, wherein the texture value patch type is incompatible signs, gamma, depth, or bias; and
based on the second GPU state data, applying a texture value patch of the texture value patch type to the one or more binary instructions, wherein applying the texture value patch translates the one or more binary instructions into one or more translated binary instructions configured to be executed on the second GPU.

11. The method of claim 10 , wherein
each texture fetch of the one or more texture fetches indicates a texture to be displayed on a display.

12. The method of claim 11 , wherein the texture value patch is an incompatible signs texture value patch configured to translate a texture fetch into a plurality of translated texture fetches.

13. The method of claim 11 , wherein the texture value patch is a gamma patch configured to convert fetched texture values that are gamma encoded according to a first gamma correction curve of the first GPU and processed in hardware by the second GPU as if they were encoded according to the second gamma correction curve to corrected texture values that are linear or near linear encoded in a first linear encoding space of the first GPU.

14. The method of claim 11 , wherein the texture fetch constant further includes one or more of a data format, texture edge data, and channel order data.

15. The method of claim 10 , wherein the one or more global properties of the second GPU include an instruction set architecture (ISA) of the second GPU and/or an application binary interface (ABI) of the second GPU.

16. The method of claim 10 , wherein the method further comprises receiving first GPU state data that indicates one or more global properties of the first GPU including an instruction set architecture (ISA) of the first GPU and/or an application binary interface (ABI) of the first GPU, and wherein the texture value patch is applied based at least in part on the one or more global properties of the first GPU.

17. A computing system configured to execute instructions for a first graphical processing unit (GPU) on a second GPU, the computing system comprising:
the second GPU;
a display; and
a processor configured to:
receive first GPU state data that indicates one or more global properties of the first GPU;
receive second GPU state data that indicates one or more global properties of the second GPU;
receive one or more binary instructions for texture operations configured for the first GPU, wherein:
the one or more binary instructions for texture operations include one or more texture fetches,
each texture fetch includes a texture fetch constant having a respective sign for each of one or more channels that encode coordinates for the texture fetch, and
each texture fetch of the one or more texture fetches indicates a texture to be displayed on the display;

determine a texture value patch type based at least in part on the one or more signs included in the one or more binary instructions, wherein the texture value patch type is incompatible signs, gamma, depth, or bias; and
based on the first GPU state data and the second GPU state data, apply a texture value patch of the texture value patch type to the one or more binary instructions, wherein applying the texture value patch translates the one or more binary instructions into one or more translated binary instructions configured to be executed on the second GPU.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Stover Aaron Blake
• Gordon Matthew
• Heutchy Eric David
• Deng Ke
• Burch Warren Lee
• Perkins Roger John

Classifications

• G06F9/4552

  Involving translation to a different instruction set architecture, e.g. just-in-time translation in a JVM · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title