Deep learning testability analysis with graph convolutional networks

Patent metadata

Field	Value
Publication number	US-10657306-B1
Application number	US-201916520688-A
Country	US
Kind code	B1
Filing date	Jul 24, 2019
Priority date	Nov 9, 2018
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

First claim

What is claimed is:

1. A method for inserting test logic into a circuit, the method comprising:
forming a graph representation from a netlist for the circuit;
forming a node embedding for the netlist by processing the graph through a series of aggregators and encoders;
applying the node embedding to a deep neural network classifier to generate predictions of whether nodes of the circuit are difficult to test nodes; and
inserting the test logic into the circuit at the difficult to test nodes.

2. The method of claim 1 , further comprising:
computing a testability impact for the test logic; and
inserting the test logic only when the testability impact satisfies a threshold.

3. The method of claim 2 , the testability impact computed for a local neighborhood around a node predicted to be a difficult to test node.

4. The method of claim 1 , further comprising:
transforming the netlist into a levelized netlist; and
processing the levelized netlist through the series of aggregators and encoders.

5. The method of claim 1 , the deep neural network further generating predictions of whether the nodes of the circuit are non-difficult to test nodes.

6. The method of claim 1 , further comprising:
setting controllability-to-0, controllability-to-1, and observability as attributes of the node embedding.

7. The method of claim 6 , the attributes derived using a Sandia Controllability and Observability (SCOAP) algorithm.

8. The method of claim 1 , the node embedding derived from a D-hop local neighborhood of each node in the graph.

9. The method of claim 8 , where D=2.

10. The method of claim 1 , the graph being a directed acyclic graph.

11. The method of claim 1 , further comprising:
transforming the graph into an adjacency matrix mapping weights of the deep neural network to connections of the graph.

12. A system to direct the insertion of test logic into a circuit, the system comprising:
at least one graphic processing unit; and
a memory configured with instructions that when applied to the at least one graphics processing unit, configure the at least one graphic processing unit to:
transform a netlist representation of the circuit into a node embedding using a series of aggregators and encoders;
generate predictions, based at least in part on characteristics of a local neighborhood of a node in the circuit represented in the node embedding, of whether the node corresponds to a difficult to test node or non-difficult to test node in the circuit; and
on condition that the node is predicted to be a difficult to test node, modify the circuit with test logic at the node.

13. The system of claim 12 , the instructions further configuring the at least one graphics processing unit to apply the modified circuit to generate a manufacturing layout.

14. The system of claim 12 , the instructions further:
configuring each of multiple graphics processing units to generate the prediction on a portion of the circuit; and
assign a particular one of the multiple graphics processing units to perform backpropagation of errors in the predictions.

15. The system of claim 12 , the instructions further configuring the at least one graphics processing unit to prune nodes that are not difficult to test nodes during each iteration of generating the predictions.

16. A non-transitory computer-readable storage medium, the computer-readable storage medium including instructions that when executed by a computer, cause the computer to:
generate a levelized netlist of a circuit;
form a graph representation of the levelized netlist;
form node embeddings for nodes of the graph by processing the nodes through a series of aggregators and encoders;
apply the node embedding to a classifier to generate predictions of whether the nodes are difficult to test nodes; and
on condition that a node of the nodes is classified as a difficult to test node, insert a test node adjacent to the node in the graph.

17. The non-transitory computer-readable storage medium of claim 16 , the instructions further causing the computer to:
compute a testability impact for the test node; and
inserting the test node only when the testability impact satisfies a threshold.

18. The non-transitory computer-readable storage medium of claim 16 , the instructions further causing the computer to:
set controllability-to-0, controllability-to-1, and observability as attributes of the node embedding.

19. The non-transitory computer-readable storage medium of claim 16 , the instructions further causing the computer to:
transform the graph into an adjacency matrix mapping weights of a deep neural network to connections of the graph.

20. The non-transitory computer-readable storage medium of claim 19 , the instructions further causing the computer to:
generate the adjacency matrix in a sparse coordinate form.

Assignees

• Nvidia Corp

Inventors

• Ma Yuzhe
• Ren Haoxing
• Khailany Brucek
• Sikka Harbinder
• Luo Lijuan
• Natarajan Karthikeyan

Classifications

• G06F30/323

  Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F30/3323

  using formal methods, e.g. equivalence checking or property checking · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/3308

  using simulation · CPC title