Circuit encoding method and circuit structure recognition method

Patent metadata

Field	Value
Publication number	US-10657303-B2
Application number	US-201815928535-A
Country	US
Kind code	B2
Filing date	Mar 22, 2018
Priority date	Apr 21, 2017
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

This invention discloses a circuit encoding method and a circuit structure recognition method. The circuit encoding method is applied to a circuit structure recognition process of a circuit. The circuit is coupled to a voltage source and a reference voltage. The circuit encoding method includes: selecting a target transistor from the circuit; when a terminal of the target transistor is electrically connected to the voltage source or the reference voltage, adding a first value to a terminal value of the terminal; when the terminal of the target transistor is electrically connected to a terminal other than the voltage source and the reference voltage, adding a second value to the terminal value of the terminal; and taking a set of multiple terminal values of the target transistor as a transistor signature of the target transistor.

First claim

What is claimed is:

1. A circuit structure recognition method, applied to a component connection description file that corresponds to a circuit and records a plurality of connections of a plurality of transistors in the circuit, the method comprising:
generating a transistor signature for each transistor, wherein the transistor signature is associated with the connections of each transistor;
dividing the circuit into a plurality of transistor groups according to a plurality of electrical connections of the drains or sources of the transistors;
generating a group signature for each transistor group according to the transistor signatures of the transistors in each transistor group;
comparing the group signatures with a predetermined group signature; and
when a target group signature of the group signatures is the same as the predetermined group signature, recognizing a target transistor group corresponding to the target group signature as a predetermined circuit sub block cell corresponding to the predetermined group signature;
wherein the circuit is coupled to a voltage source and a reference voltage, and the step of generating the transistor signature for each transistor comprises:
adding a first value to a terminal value of a terminal of a target transistor among the transistors when the terminal is electrically connected to one of the voltage source and the reference voltage; and
adding a second value to the terminal value of the terminal of the target transistor when the terminal is electrically connected to a terminal other than the voltage source and the reference voltage;
wherein the transistor signature of the target transistor is a set of a plurality of terminal values of the target transistor.

2. The method of claim 1 , wherein one of the first value and the second value is an odd number and the other is an even number.

3. The method of claim 1 , wherein the step of adding the first value to the terminal value of the terminal comprises:
adding different first values to the terminal value of the terminal when the terminal of the target transistor is electrically connected to the voltage source or the reference voltage.

4. The method of claim 1 , wherein the step of adding the second value to the terminal value of the terminal comprises:
adding different second values to the terminal value of the terminal when the terminal of the target transistor is electrically connected to the gate, the source, the drain or the bulk of any transistor.

5. The method of claim 1 , wherein the step of generating the transistor signature for each transistor further comprises:
assigning a type code to the target transistor according to the target transistor being an N-type metal-oxide semiconductor field-effect transistor or a P-type metal-oxide semiconductor field-effect transistor;
wherein the transistor signature of the target transistor is a set of the terminal values and the type code of the target transistor.

6. A circuit structure recognition method, applied to a component connection description file that corresponds to a circuit and records a plurality of connections of a plurality of transistors in the circuit, the method comprising:
generating a transistor signature for each transistor, wherein the transistor signature is associated with the connections of each transistor;
dividing the circuit into a plurality of transistor groups according to a plurality of electrical connections of the drains or sources of the transistors;
generating a group signature for each transistor group according to the transistor signatures of the transistors in each transistor group;
comparing the group signatures with a predetermined group signature; and
when a target group signature of the group signatures is the same as the predetermined group signature, recognizing a target transistor group corresponding to the target group signature as a predetermined circuit sub block cell corresponding to the predetermined group signature;
wherein the step of dividing the circuit into the transistor groups according to the electrical connections of the drains or sources of the transistors comprises:
finding a first transistor;
finding a second transistor electrically connected to the first transistor;
determining the first transistor and the second transistor to be in a same transistor group when the drain or the source of the second transistor is electrically connected to the drain or the source of the first transistor; and
determining the first transistor and the second transistor to be in different transistor groups when the gate of the second transistor is electrically connected to the drain or the source of the first transistor.

7. The method of claim 6 , wherein the circuit is coupled to a voltage source and a reference voltage, and the step of generating the transistor signature for each transistor comprises:
adding a first value to a terminal value of a terminal of a target transistor among the transistors when the terminal is electrically connected to one of the voltage source and the reference voltage; and
adding a second value to the terminal value of the terminal of the target transistor when the terminal is electrically connected to a terminal other than the voltage source and the reference voltage;
wherein the transistor signature of the target transistor is a set of a plurality of terminal values of the target transistor.

8. The method of claim 7 , wherein one of the first value and the second value is an odd number and the other is an even number.

9. The method of claim 7 , wherein the step of adding the first value to the terminal value of the terminal comprises:
adding different first values to the terminal value of the terminal when the terminal of the target transistor is electrically connected to the voltage source or the reference voltage.

10. The method of claim 7 , wherein the step of adding the second value to the terminal value of the terminal comprises:
adding different second values to the terminal value of the terminal when the terminal of the target transistor is electrically connected to the gate, the source, the drain or the bulk of any transistor.

11. The method of claim 7 , wherein the step of generating the transistor signature for each transistor further comprises:
assigning a type code to the target transistor according to the target transistor being an N-type metal-oxide semiconductor field-effect transistor or a P-type metal-oxide semiconductor field-effect transistor;
wherein the transistor signature of the target transistor is a set of the terminal values and the type code of the target transistor.

Assignees

• Realtek Semiconductor Corp

Inventors

• Lin Yun-Jing
• Lee Meng-Jung
• Lo Yu-Lan
• Kao Shu-Yi
• Liu Chien-Nan
• Lou Yu-Kang
• Lin Ching-Ho

Classifications

• G06F30/3323

  using formal methods, e.g. equivalence checking or property checking · CPC title

• G06F30/36 Primary

  Circuit design at the analogue level · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F2111/20

  Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules · CPC title