Security for programmable devices in a data center

Patent metadata

Field	Value
Publication number	US-10657292-B2
Application number	US-201715845958-A
Country	US
Kind code	B2
Filing date	Dec 18, 2017
Priority date	Dec 18, 2017
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

An example method of configuring a programmable integrated circuit (IC) in a computer system includes: selecting a first region of a programmable fabric of the programmable IC for implementation of a shell circuit, the shell circuit configured to interface with a bus of the computer system; selecting a second region of the programmable fabric for implementation of an application circuit, the application circuit configured to interface with the shell circuit; providing a fence region disposed between the first region and the second region, the fence region including a set of un-configured tiles of the programmable fabric; generating configuration data for a circuit design having the first region, the second region, and the fence region; and loading the configuration data to the programmable IC.

First claim

What is claimed is:

1. A method of configuring a programmable integrated circuit (IC) in a computer system, comprising:
selecting a first region of a programmable fabric of the programmable IC for implementation of a shell circuit, the shell circuit configured to interface with a bus of the computer system;
selecting a second region of the programmable fabric for implementation of an application circuit, the application circuit configured to interface with the shell circuit;
providing a fence region disposed between the first region and the second region, the fence region including a set of un-configured tiles of the programmable fabric;
generating configuration data for a circuit design having the first region, the second region, and the fence region; and
loading the configuration data to the programmable IC.

2. The method of claim 1 , wherein the application circuit is coupled to the shell circuit using connections through the fence region.

3. The method of claim 2 , wherein logic and routing of the application circuit is contained within the second region, wherein logic and routing of the shell circuit is contained in the first region, and wherein input/output (10) ports of the application circuit are coupled to 10 ports of the shell circuit by the connections.

4. The method of claim 1 , further comprising:
selecting a third region of the programmable fabric for implementation of global clock logic configured to provide clock signals to the shell circuit and the application circuit.

5. The method of claim 1 , wherein the shell circuit includes a system monitor configured monitor the programmable IC and to signal the computer system in response to detecting an error condition.

6. The method of claim 1 , wherein the shell circuit includes a run-time checking circuit configured to readback configuration data of the programmable IC and verify integrity of the first region, the second region, and the fence region.

7. The method of claim 6 , wherein the run-time checking circuit is coupled to an internal configuration access port of the programmable IC.

8. A non-transitory computer readable medium having stored thereon instructions that when executed by a processor cause the processor to perform a method of configuring a programmable integrated circuit (IC) in a computer system, comprising:
selecting a first region of a programmable fabric of the programmable IC for implementation of a shell circuit, the shell circuit configured to interface with a bus of the computer system;
selecting a second region of the programmable fabric for implementation of an application circuit, the application circuit configured to interface with the shell circuit;
providing a fence region disposed between the first region and the second region, the fence region including a set of un-configured tiles of the programmable fabric;
generating configuration data for a circuit design having the first region, the second region, and the fence region; and
loading the configuration data to the programmable IC.

9. The non-transitory computer readable medium of claim 8 , wherein the application circuit is coupled to the shell circuit using connections through the fence region.

10. The non-transitory computer readable medium of claim 9 , wherein logic and routing of the application circuit is contained within the second region, wherein logic and routing of the shell circuit is contained in the first region, and wherein input/output (10) ports of the application circuit are coupled to 10 ports of the shell circuit by the connections.

11. The non-transitory computer readable medium of claim 8 , further comprising:
selecting a third region of the programmable fabric for implementation of global clock logic configured to provide clock signals to the shell circuit and the application circuit.

12. The non-transitory computer readable medium of claim 8 , wherein the shell circuit includes a system monitor configured monitor the programmable IC and to signal the computer system in response to detecting an error condition.

13. The non-transitory computer readable medium of claim 8 , wherein the shell circuit includes a run-time checking circuit configured to readback configuration data of the programmable IC and verify integrity of the first region, the second region, and the fence region.

14. The non-transitory computer readable medium of claim 13 , wherein the run-time checking circuit is coupled to an internal configuration access port of the programmable IC.

15. A computing system, comprising:
a processing system;
a hardware accelerator coupled to the processing system, the hardware accelerator including:
a programmable integrated circuit (IC) configured with an acceleration circuit having a first region of a programmable fabric for implementation of a shell circuit, the shell circuit configured to interface with a bus of the processing system, a second region for implementation of an application circuit, the application circuit configured to interface with the shell circuit, and a fence region disposed between the first region and the second region, the fence region including a set of un-configured tiles of the programmable fabric;

a software platform executing on the processing system, the software platform including program code executable by the processing system to interface with the hardware accelerator.

16. The computing system of claim 15 , wherein the application circuit is coupled to the shell circuit using connections through the fence region.

17. The computing system of claim 16 , wherein logic and routing of the application circuit is contained within the second region, wherein logic and routing of the shell circuit is contained in the first region, and wherein input/output (10) ports of the application circuit are coupled to 10 ports of the shell circuit by the connections.

18. The computing system of claim 15 , wherein the shell circuit includes a system monitor configured monitor the programmable IC and to signal the computer system in response to detecting an error condition.

19. The computing system of claim 15 , wherein the shell circuit includes a run-time checking circuit configured to readback configuration data of the programmable IC and verify integrity of the first region, the second region, and the fence region.

20. The computing system of claim 19 , wherein the run-time checking circuit is coupled to an internal configuration access port of the programmable IC.

Assignees

• Xilinx Inc

Inventors

• Trimberger Stephen M

Classifications

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F21/76 Primary

  in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F15/7867 Primary

  with reconfigurable architecture · CPC title

• G06F17/5054

  Physics · mapped topic