Latency test in networking system-on-chip verification

Patent metadata

Field	Value
Publication number	US-10657217-B2
Application number	US-201715792124-A
Country	US
Kind code	B2
Filing date	Oct 24, 2017
Priority date	Oct 25, 2016
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

Aspects of the disclosed technology relate to techniques of latency test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates arrival time information with messages when the messages are delivered to a hardware model of a circuit design implemented in the reconfigurable hardware modeling device, and associates latency information with the messages when the messages are dispatched by the hardware model of the circuit design. The arrival time information of a particular message and the latency information are determined with respect to a model time reference provided in the reconfigurable hardware modeling device.

First claim

What is claimed is:

1. A method, comprising:
associating, by a hardware model of interface circuitry implemented in a reconfigurable hardware modeling device, arrival time information with messages when the messages are delivered to a hardware model of a circuit design implemented in the reconfigurable hardware modeling device, the arrival time information of a particular message including information about when, based on a model time reference provided in the reconfigurable hardware modeling device, the particular message is delivered to the hardware model of the circuit design, wherein the associating arrival time information with messages comprises inserting the arrival time information of each of the messages in a metadata field of or a data field of the each of the messages or in special messages;
associating, by the hardware model of the interface circuitry, latency information with the messages when the messages are dispatched by the hardware model of the circuit design, the latency information being determined based on the model time reference and the arrival time information; and
sending the messages and the latency information to a traffic analysis device.

2. The method recited in claim 1 , wherein the associating latency information with the messages comprises:
inserting the latency information of each of the messages in a metadata field of or a data field of the each of the messages or in special messages.

3. The method recited in claim 1 , wherein the associating latency information with the messages comprises:
replacing the arrival time information with the latency information.

4. The method recited in claim 1 , wherein the sending comprises:
sending the arrival time information along with the messages and the latency information to the traffic analysis device.

5. The method recited in claim 4 , further comprising:
determining, by the traffic analysis device, dispatch time information based on the arrival time information and the latency information, the dispatch time information of a particular message including information about when, based on the model time reference, the particular message is dispatched by the hardware model of the circuit design; and
determining, by the traffic analysis device, bandwidth information of ports of the circuit design based on the dispatch time information.

6. The method recited in claim 1 , further comprising:
associating, by the hardware model of the interface circuitry, dispatch time information with the messages when the messages are dispatched by the hardware model of the circuit design, the dispatch time information of a particular message including information about when, based on the model time reference, the particular message is dispatched by the hardware model of the circuit design, wherein the sending comprises sending the dispatch time information along with the messages and the latency information to the traffic analysis device.

7. The method recited in claim 1 , wherein the hardware model of the interface circuitry converts the messages from transaction-level messages to signal-level messages before delivering the messages to the hardware model of the circuit design and converts the messages from signal-level messages to transaction-level messages before sending the messages to the traffic analysis device.

8. The method recited in claim 1 , wherein the reconfigurable hardware modeling device is a hardware-based emulator or an FPGA-based prototyping device.

9. The method recited in claim 1 , wherein the traffic analysis device is implemented at least in part by a network traffic tool, the network traffic tool being implemented by a virtual machine running on a computer.

10. The method recited in claim 1 , wherein the circuit design is a design for a network switch, a router, a network processor, or a network gateway.

11. The method recited in claim 1 , wherein the model time reference is provided at least in part by a multi-bit register in the reconfigurable hardware modeling device.

12. One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to generate bitstreams for programming a reconfigurable hardware modeling device to implement circuitry hardware models, the circuitry hardware models comprising:
a hardware model of a circuit design, and
a hardware model of interface circuitry configurable to associate arrival time information with messages when the messages are delivered to the hardware model of the circuit design and to associate latency information with the messages when the messages are dispatched by the hardware model of the circuit design, the arrival time information of a particular message including information about when, based on a model time reference provided in the reconfigurable hardware modeling device, the particular message is delivered to the hardware model of the circuit design, the latency information being determined based on the model time reference and the arrival time information, wherein the association of the arrival time information with the messages comprises inserting the arrival time information of each of the messages in a metadata field of or a data field of the each of the messages or in special messages.

13. The one or more non-transitory computer-readable media recited in claim 12 , wherein the association of the latency information with the messages comprises:
inserting the latency information of each of the messages in a metadata field of or a data field of the each of the messages or in special messages.

14. The one or more non-transitory computer-readable media recited in claim 12 , wherein the association of the latency information with the messages comprises:
replacing the arrival time information with the latency information.

15. The one or more non-transitory computer-readable media recited in claim 12 , wherein the hardware model of the interface circuitry is configurable to further associate dispatch time information with the messages when the messages are dispatched by the hardware model of the circuit design, the dispatch time information of a particular message including information about when, based on the model time reference, the particular message is dispatched by the hardware model of the circuit design, wherein the sending comprises sending the dispatch time information along with the messages and the latency information to the traffic analysis device.

16. The one or more non-transitory computer-readable media recited in claim 12 , wherein the arrival time information and the latency information are used to determine bandwidth information of ports of the circuit design by a traffic analysis device that receives the messages from the reconfigurable hardware modeling device.

17. The one or more non-transitory computer-readable media recited in claim 12 , wherein the hardware model of the interface circuitry is configurable to further convert the messages from transaction-level messages to signal-level messages before delivering the messages to the hardware model of the circuit design and to further convert the messages from signal-level messages to transaction-level messages before sending the messages to a traffic analysis device.

18. The one or more non-transitory computer-readable media recited in claim 12 , wherein the reconfigurable hardware modeling device is a hardware-based emulator or an FPGA-based prototyping device.

19. The one or more non-transitory computer-readable media recited in claim 12 , wherein the circuit design is a desig

Assignees

• Mentor Graphics Corp

Inventors

• Krishnamurthy Suresh
• Garg Deepak Kumar
• Jayaswal Sudhanshu
• Khaitan Saurabh
• Gupta Sanjay
• Stickley John R
• Vreeland Iii Russell Elias
• Squiers Ronald James
• Das Abhijit
• Selvidge Charles W

Classifications

• G06F30/30

  Circuit design · CPC title

• G06F13/1673 Primary

  using buffers · CPC title

• G06F11/221

  to test buses, lines or interfaces, e.g. stuck-at or open line faults · CPC title

• G06F30/331

  with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation · CPC title

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title