Interruption facility for adjunct processor queues

Patent metadata

Field	Value
Publication number	US-10657085-B2
Application number	US-201916519142-A
Country	US
Kind code	B2
Filing date	Jul 23, 2019
Priority date	Oct 21, 2008
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions.

First claim

What is claimed is:

1. A computer-implemented method of facilitating processing within a computing environment, the computer-implemented method of comprising:
determining that a queue of the computing environment has transitioned from a no replies pending state to a reply pending state, wherein the queue is indirectly accessible to user programs in that it is located in memory having addresses unaware to the user programs and in which a central processing unit is to use a specific limited instruction to place a request on the queue to be removed by an adjunct processor that performs work for the central processing unit and has direct access to the queue, and wherein the no replies pending state is a state in which the queue is empty of replies, and the reply pending state is a state in which the queue is not empty of replies; and
initiating an interrupt for the queue based on determining that the queue has transitioned from the no replies pending state to the reply pending state and based on the queue being enabled for interrupts.

2. The computer-implemented method of claim 1 , wherein the interrupt is not initiated based on the queue not transitioning from the no replies pending state to the reply pending state.

3. The computer-implemented method of claim 1 , wherein the queue is enabled for interrupts via a process adjunct processor queue (PQAP) instruction.

4. The computer-implemented method of claim 3 , wherein the PQAP instruction employs general registers 0, 1 and 2 for input, and general register 1 for output.

5. The computer-implemented method of claim 4 , wherein, for input, general register 0 includes a function code indicating an interruption control and a queue number designating the queue to be processed, general register 1 includes an interruption request indicator specifying enablement or disablement of the queue, and general register 2 includes an address of a notification indicator.

6. The computer-implemented method of claim 5 , wherein, for input, general register 1 further includes an indication of an interruption subclass.

7. The computer-implemented method of claim 4 , wherein, for output, general register 1 includes a status indicator providing status relating to execution of the PQAP instruction.

8. The computer-implemented method of claim 1 , further comprising placing a reply to the request on the queue when the queue is in the no replies pending state, transitioning the queue from the no replies pending state to the reply pending state.

9. The computer-implemented method of claim 1 , wherein the request comprises a cryptographic request.

10. The computer-implemented method of claim 1 , wherein the queue is an adjunct processor queue, and wherein the initiating is performed by the adjunct processor.

Assignees

• IBM

Inventors

• Gainey Jr Charles W
• Meissner Klaus
• Osisek Damian L
• Werner Klaus

Classifications

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title