Control device for a motor vehicle

Patent metadata

Field	Value
Publication number	US-10657039-B2
Application number	US-201415100393-A
Country	US
Kind code	B2
Filing date	Oct 13, 2014
Priority date	Dec 3, 2013
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A control device for a motor vehicle, the control device including at least two processor cores and a global memory, each processor core respectively including a local memory and each processor core being set up to access only its own local memory and being set up to access neither the local memories of the other processor cores nor the global memory, a coordination unit being set up to read in data from the global memory of the control device and to write it to the local memories of the individual processor cores, and to read in data from the local memories of the individual processor cores and to write it to the global memory and/or to the local memory of the other processor cores.

First claim

What is claimed is:

1. A control device, comprising:
a multicore processor having at least two processor cores;
a global memory, wherein each of the processor cores respectively includes a local memory, each of the processor cores being configured to access only its own local memory, and each of the processor cores being configured so that it cannot access the local memories of the others of the processor cores and being configured so that it cannot access the global memory; and
a coordination unit configured to: (i) transfer data, in accordance with a sequence plan available to the coordination unit, from the global memory of the control device, directly without intermediate storage, to the local memories of the processor cores, and (ii) transfer data, in accordance with the sequence plan available to the coordination unit, from the local memories of individual ones of the processor cores, directly without intermediate storage, to at least one of: the global memory or the local memory of another of the processor cores;
wherein the coordination unit is configured to: (i) assign a task to each of the at least two processor cores in accordance with the sequence plan available to the coordination unit, and/or (ii) instruct each of the at least two processor cores to perform the task in accordance with the sequence plan available to the coordination unit;
wherein the coordination unit includes a controller or a processor;
wherein the coordination unit coordinates a data exchange between the local memories of the processor cores of the multicore processor and the global memory, as well as a data exchange between the local memories of the processor cores of the multicore processor, among one another, so as to prevent an occurrence of data access collisions,
wherein the coordination unit is configured to run software, and is networked via a bus with the processor cores of the multicore processor.

2. The control device as recited in claim 1 , wherein the coordination unit is configured to execute the transfer of data from the global memory by transferring to the local memories of the processor cores at least one of: i) a program code of a task that is to be executed, and ii) input data required for a task that is to be executed, directly without intermediate storage to the local memory of the processor cores.

3. The control device as recited in claim 1 , wherein the coordination unit is configured to transfer output data, stored by a processor core in its local memory after executing a task, from this local memory, directly without intermediate storage to at least one of: i) the global memory, and ii) the local memory of one of the other processor cores.

4. The control device as recited in claim 1 , wherein the coordination unit is configured to at least one of: i) assign tasks that are to be executed to each of the processor cores, and ii) instruct each of the processor cores to execute specified tasks.

5. The control device as recited in claim 1 , wherein at least one of: i) the coordination unit is configured to instruct a plurality of processor cores to execute a specified task and to compare the individual output data of the processor cores with one another, and ii) the coordination unit is configured to instruct a processor core to execute a specified task multiple times and to compare the individual output data of this multiple execution by the processor core with one another.

6. The control device as recited in claim 1 , wherein the coordination unit is configured to control each of the processor cores and in the course thereof to at least one of: i) interrupt the individual processor cores, ii) reset them, iii) take them out of operation, iv) test them, v) put them into a power saving mode, vi) trigger an interrupt at the processor cores, and vii) modify a clock frequency of the processor cores.

7. The control device as recited in claim 1 , wherein the individual local memories of the processor cores are each divided into different memory banks, and the coordination unit is configured to control which memory banks the respective processor core is permitted to access.

8. The control device as recited in claim 1 , wherein the coordination unit is realized either as a part of a processor core, or as a separate hardware element.

9. The control device as recited in claim 1 , wherein the control device is for a motor vehicle.

10. The control device as recited in claim 1 , wherein: (i) the transfer of data from the global memory of the control device, directly without intermediate storage, to the local memory of each of the processor cores, by the coordination unit is independent of the processor cores, and (ii) wherein the transfer of data from the local memories of the individual ones of the processor cores, directly without intermediate storage, to the at least one of: the global memory or the local memories of the other processor cores, by the coordination unit, is independent of the processor cores.

11. A control device, comprising:
a multicore processor having at least two processor cores;
a global memory, wherein each of the processor cores respectively includes a local memory, each of the processor cores being configured to access only its own local memory, and each of the processor cores being configured so that it cannot access the local memories of the others of the processor cores and being configured so that it cannot access the global memory; and
a coordination unit configured to: (i) transfer data, independent of the processor cores and in accordance with a sequence plan available to the coordination unit, from the global memory of the control device to the local memories of the processor cores, and (ii) transfer data, independent of the processor cores and in accordance with the sequence plan available to the coordination unit, from the local memories of individual ones of the processor cores to at least one of: the global memory, or the local memory of another of the processor cores;
wherein the coordination unit is configured to: (i) assign a respective task to each of the at least two processor cores in accordance with the sequence plan available to the coordination unit, and/or (ii) instruct each of the at least two processor cores to perform the respective task in accordance with the sequence plan available to the coordination unit;
wherein the coordination unit includes a controller or a processor;
wherein the coordination unit coordinates a data exchange between the local memories of the processor cores of the multicore processor and the global memory, as well as a data exchange between the local memories of the processor cores of the multicore processor, among one another, so as to prevent an occurrence of data access collisions,
wherein the coordination unit is configured to run software, and is networked via a bus with the processor cores of the multicore processor.

12. The control device as recited in claim 11 , wherein the coordination unit is configured to execute the transfer of the data from the global memory, and the transfer of the data from the local memories of the individual ones of the processor cores, in at least one of: i) an application-specific manner, and ii) in a time-driven manner.

13. The control device as recited in claim 11 , wherein the coordination unit is configured to execute the transfer of the data from the global memory to the local memories of the processor cores by transferring at least one of: i) a program code of a task that is to be executed, and ii) input data required for a task that is to be executed.

14. The control device as recited in claim 11 , wherein the coordination unit is co

Assignees

• Bosch Gmbh Robert

Inventors

• Biewer Alexander
• Thoss Dieter
• Gladigau Jens
• Haubelt Christian

Classifications

• G06F2212/251

  Local memory within processor subsystem · CPC title

• G06F15/167

  using a common memory, e.g. mailbox · CPC title

• G06F15/17325

  Synchronisation; Hardware support therefor (intertask synchronisation G06F9/52) · CPC title

• G06F12/023 Primary

  Free address space management · CPC title

• G06F12/06

  Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence) · CPC title