Method and apparatus to rollback memory DIMM lane sparing

Patent metadata

Field	Value
Publication number	US-10657002-B2
Application number	US-201715809566-A
Country	US
Kind code	B2
Filing date	Nov 10, 2017
Priority date	Nov 10, 2017
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A method for correcting improper repair actions in a computer system includes assigning a first algorithm identifier to a first algorithm and storing the first algorithm identifier and a first input to the first algorithm. The method includes executing the first algorithm with the first input and storing one or more results of the first algorithm, where the one or more results includes a repair action. The method includes determining that the repair action is faulty and storing the algorithm identifier for the first algorithm in a blacklist. The method also includes assigning a second algorithm identifier to a second algorithm and storing the second algorithm identifier and a second input to the second algorithm. The method includes executing the second algorithm with the second input, where the second algorithm corrects the faulty repair action caused by the first algorithm, and storing a result of the second algorithm.

First claim

What is claimed is:

1. A method for correcting improper repair actions in a computer system, comprising:
assigning a first algorithm identifier to a first algorithm;
storing the first algorithm identifier and a first input to the first algorithm;
executing, via a processor, the first algorithm with the first input and storing one or more results of the first algorithm, wherein the one or more results comprises a repair action;
determining that the repair action is faulty;
storing the algorithm identifier for the first algorithm in a blacklist;
assigning a second algorithm identifier to a second algorithm;
storing the second algorithm identifier and a second input to the second algorithm;
executing, via the processor, the second algorithm with the second input, wherein the second algorithm corrects the faulty repair action caused by the first algorithm; and
storing a result of the second algorithm.

2. The method of claim 1 , wherein the repair action further comprises a memory lane sparing action.

3. The method of claim 1 , further comprising:
storing the second algorithm identifier, the second input, and the result of the second algorithm in serial presence data on a memory chip.

4. The method of claim 3 , further comprising:
commencing a system boot sequence that includes the second algorithm;
determining if the second input to the second algorithm has changed;
if the second input has not changed, skipping the execution of the second algorithm and reading a cached result of a previous iteration of the second algorithm; and
continuing the boot sequence.

5. The method of claim 3 , further comprising:
commencing a system boot sequence that includes the second algorithm;
determining if the second input to the second algorithm has changed;
if the second input has changed, execute the second algorithm and store a result of the second algorithm; and
continue the boot sequence.

6. The method of claim 1 , wherein the second algorithm is executed as a portion of a firmware update on the computer system.

7. The method of claim 1 , further comprising:
commencing a system boot sequence;
retrieving repair information, the second algorithm identifier, and the second input;
if the second algorithm ID is on the blacklist, undo any repair actions as a result of the second algorithm and set a flag for diagnostics of the computer system.

8. The method of claim 1 , further comprising:
After storing the result of the second algorithm, running a diagnostic to verify the faulty repair action has been corrected.

9. The method of claim 1 , wherein the second algorithm is executed for each memory component in the computer system.

10. The method of claim 1 , wherein a checksum is stored for each of the first input and the second input.

11. A system, comprising:
a processor; and
a memory storing a program, which, when executed on the processor, performs an operation for correcting improper repair actions, the operation comprising:
assigning a first algorithm identifier to a first algorithm;
storing the first algorithm identifier and a first input to the first algorithm;
executing, via a processor, the first algorithm with the first input and storing one or more results of the first algorithm, wherein the one or more results comprises a repair action;
determining that the repair action is faulty;
storing the algorithm identifier for the first algorithm in a blacklist;
assigning a second algorithm identifier to a second algorithm;
storing the second algorithm identifier and a second input to the second algorithm;
executing, via the processor, the second algorithm with the second input, wherein the second algorithm corrects the faulty repair action caused by the first algorithm; and
storing a result of the second algorithm.

12. The system of claim 11 , wherein the repair action further comprises a memory lane sparing action.

13. The system of claim 11 , the operation further comprising:
storing the second algorithm identifier, the second input, and the result of the second algorithm in serial presence data on a memory chip.

14. The system of claim 13 , the operation further comprising:
commencing a system boot sequence that includes the second algorithm;
determining if the second input to the second algorithm has changed;
if the second input has not changed, skipping the execution of the second algorithm and reading a cached result of a previous iteration of the second algorithm; and
continuing the boot sequence.

15. The system of claim 13 , the operation further comprising:
commencing a system boot sequence that includes the second algorithm;
determining if the second input to the second algorithm has changed;
if the second input has changed, execute the second algorithm and store a result of the second algorithm; and
continue the boot sequence.

16. A computer program product for correcting improper repair actions, the computer program product comprising a computer-readable medium program having program instructions embodied therewith, the program instructions executable by a processor to perform an operation comprising:
assigning a first algorithm identifier to a first algorithm;
storing the first algorithm identifier and a first input to the first algorithm;
executing, via a processor, the first algorithm with the first input and storing one or more results of the first algorithm, wherein the one or more results comprises a repair action;
determining that the repair action is faulty;
storing the algorithm identifier for the first algorithm in a blacklist;
assigning a second algorithm identifier to a second algorithm;
storing the second algorithm identifier and a second input to the second algorithm;
executing, via the processor, the second algorithm with the second input, wherein the second algorithm corrects the faulty repair action caused by the first algorithm; and
storing a result of the second algorithm.

17. The computer program product of claim 16 , wherein the repair action further comprises a memory lane sparing action.

18. The computer program product of claim 16 , the operation further comprising:
storing the second algorithm identifier, the second input, and the result of the second algorithm in serial presence data on a memory chip.

19. The computer program product of claim 18 , the operation further comprising:
commencing a system boot sequence that includes the second algorithm;
determining if the second input to the second algorithm has changed;
if the second input has not changed, skipping the execution of the second algorithm and reading a cached result of a previous iteration of the second algorithm; and
continuing the boot sequence.

20. The computer program product of claim 18 , the operation further comprising:
commencing a system boot sequence that includes the second algorithm;
determining if the second input to the second algorithm has changed;
if the second input has changed, execute the second algorithm and store a result of the second algorithm; and
continue the boot sequence.

Assignees

• IBM

Inventors

• Bofferding Nicholas E
• Geissler Andrew J
• Hollinger Michael C
• Kobylak Adriana

Classifications

• G06F11/1417

  Boot up procedures · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G11C29/4401

  for self repair · CPC title

• G06F11/2025

  using centralised failover control functionality · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title