Next instruction access intent instruction for indicating usage of a storage operand by one or more instructions subsequent to a next sequential instruction

Patent metadata

Field	Value
Publication number	US-10656945-B2
Application number	US-201213524105-A
Country	US
Kind code	B2
Filing date	Jun 15, 2012
Priority date	Jun 15, 2012
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

Executing a Next Instruction Access Intent instruction by a computer. The processor obtains an access intent instruction indicating an access intent. The access intent is associated with an operand of a next sequential instruction. The access intent indicates usage of the operand by one or more instructions subsequent to the next sequential instruction. The computer executes the access intent instruction. The computer obtains the next sequential instruction. The computer executes the next sequential instruction, whose execution comprises, based on the access intent, adjusting one or more cache behaviors for the operand of the next sequential instruction.

First claim

What is claimed is:

1. A computer system comprising:
a memory; and
a processor in communication with said memory, said processor comprising an instruction fetching unit for fetching instructions from the memory and one or more execution units for executing fetched instructions;
wherein said computer system is configured to perform a method comprising:
obtaining an access intent instruction, said access intent instruction comprising an access intent operand indicating an access intent for a specified storage operand as defined in a next sequential instruction, said access intent indicating usage of said storage operand by one or more instructions subsequent to said next sequential instruction;
executing said access intent instruction, said executing of said access intent instruction comprising signaling to the processor executing said access intent instruction the access intent indicated for the specified storage operand of said next sequential instruction;
obtaining the next sequential instruction; and
executing said next sequential instruction, said executing said next sequential instruction comprising:
based on said access intent, adjusting one or more actions directed at caching for said storage operand of said next sequential instruction, wherein:
a first value of the access intent operand signals to the processor that the storage operand of said next sequential instruction may or may not be accessed as an instruction operand by said one or more instructions subsequent to said next sequential instruction;
a second value of the access intent operand signals to the processor that the storage operand of said next sequential instruction will be accessed by said one or more instructions subsequent to said next sequential instruction for operand store access and may also be accessed for operand fetch access;
a third value of the access intent operand signals to the processor that the storage operand of said next sequential instruction will be accessed by said one or more instructions subsequent to said next sequential instruction for operand fetch access; and
a fourth value of the access intent operand signals to the processor that the storage operand of said next sequential instruction will not be accessed as an instruction operand by said one or more instructions subsequent to said next sequential instruction.

2. The computer system according to claim 1 , wherein the method further comprises storing said access intent in an internal control register.

3. The computer system according to claim 1 , wherein said access intent instruction indicates a second access intent, said second access intent being associated with a second storage operand of said next sequential instruction, said second access intent indicating usage of said second storage operand by said one or more instructions subsequent to said next sequential instruction.

4. The computer system according to claim 1 , wherein based on said access intent, adjusting one or more actions directed at caching for said storage operand of said next sequential instruction further comprises:
based on said access intent being a first access intent, adjusting a recently used state of an accessed cache line to be at or near least recently used; and
based on said access intent being a second access intent, not adjusting the recently used state of the accessed cache line to be most recently used.

5. The computer system according to claim 1 , wherein based on said access intent, adjusting one or more actions directed at caching for said storage operand of said next sequential instruction further comprises:
based on a cache miss and said access intent, requesting a cache line to be read-only or exclusive from a next higher level cache.

6. The computer system according to claim 1 , wherein said computer system further comprises a co-processor.

7. The computer system according to claim 1 , wherein said one or more actions directed at caching comprise requesting a cache line.

8. The computer system according to claim 1 , wherein said one or more actions directed at caching comprise modifying a recently used state of an accessed cache line.

9. A computer program product comprising:
a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for performing a method comprising:
obtaining an access intent instruction, said access intent instruction comprising an access intent operand indicating an access intent for a specified storage operand as defined in a next sequential instruction, said access intent indicating usage of said storage operand by one or more instructions subsequent to said next sequential instruction;
executing said access intent instruction, said executing of said access intent instruction comprising signaling to a processor executing said access intent instruction the access intent indicated for the specified storage operand of said next sequential instruction;
obtaining the next sequential instruction; and
executing said next sequential instruction, said executing said next sequential instruction comprising:
based on said access intent, adjusting one or more actions directed at caching for said storage operand of said next sequential instruction, wherein:
a first value of the access intent operand signals to the processor that the storage operand of said next sequential instruction may or may not be accessed as an instruction operand by said one or more instructions subsequent to said next sequential instruction;
a second value of the access intent operand signals to the processor that the storage operand of said next sequential instruction will be accessed by said one or more instructions subsequent to said next sequential instruction for operand store access and may also be accessed for operand fetch access;
a third value of the access intent operand signals to the processor that the storage operand of said next sequential instruction will be accessed by said one or more instructions subsequent to said next sequential instruction for operand fetch access; and
a fourth value of the access intent operand signals to the processor that the storage operand of said next sequential instruction will not be accessed as an instruction operand by said one or more instructions subsequent to said next sequential instruction.

10. The computer program product according to claim 9 , wherein the method further comprises storing said access intent in an internal control register.

11. The computer program product according to claim 10 , wherein said processing circuit comprises a processor and a co-processor.

12. The computer program product according to claim 9 , wherein said access intent instruction indicates a second access intent, said second access intent being associated with a second storage operand of said next sequential instruction, said second access intent indicating usage of said second storage operand by said one or more instructions subsequent to said next sequential instruction.

13. The computer program product according to claim 9 , wherein based on said access intent, adjusting one or more actions directed at caching for said storage operand of said next sequential instruction further comprises:
based on said access intent being a first access intent, adjusting a recently used state of an accessed cache line to be at or near least recently used; and
based on said access intent being a second access intent, not adjusting the recently used state of the accessed cache line to be most recently used.

14. The computer program product according to claim 9 , wherein based on said access intent, adjusting one or

Assignees

• Jacobi Christian
• Chum Chung Lung Kevin
• Slegel Timothy J
• Sittmann Iii Gustav E
• Sittmann Cynthia
• IBM

Inventors

• Jacobi Christian
• Chum Chung-Lung Kevin
• Slegel Timothy J
• Sittmann Iii Gustav E

Classifications

• G06F9/34

  Addressing or accessing the instruction operand or the result {; Formation of operand address; Addressing modes (address translation G06F12/00)} · CPC title

• G06F9/383

  Operand prefetching (cache prefetching G06F12/0862) · CPC title

• G06F12/0862 Primary

  with prefetch · CPC title

• G06F12/0815 Primary

  Cache consistency protocols · CPC title

• G06F12/126

  with special data handling, e.g. priority of data or instructions, handling errors or pinning · CPC title