Maintenance operations in a DRAM

Patent metadata

Field	Value
Publication number	US-10656851-B2
Application number	US-201916372336-A
Country	US
Kind code	B2
Filing date	Apr 1, 2019
Priority date	Jan 22, 2009
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

First claim

What is claimed is:

1. A memory controller that controls the operation of a memory device, the memory device including a command interface, an on-die termination circuit having a termination resistance, an output driver to transmit data, the output driver having an output drive strength, and a plurality of memory banks, each bank including a plurality of rows of memory cells, the memory controller comprising:
a circuit to issue a refresh command to the memory device, wherein the refresh command specifies a refresh operation of the plurality of memory banks, the refresh operation to occur during a time interval; and
the circuit to issue an operation code to the memory device, the operation code specifying a calibration operation, during the time interval, of the termination resistance of the on-die termination circuit and the output drive strength.

2. The memory controller of claim 1 , wherein the operation code is sent to the memory device with the refresh command such that the operation code is issued as part of the refresh command.

3. The memory controller of claim 1 , wherein the refresh command includes a plurality of bits to identify at least one bank as a first bank of the plurality of banks to be refreshed in a sequence in response to the refresh command.

4. The memory controller of claim 3 , wherein the refresh operation is specified as an auto-refresh operation, wherein a row of memory cells is refreshed in the at least one bank identified by the plurality of bits.

5. The memory controller of claim 1 , wherein the circuit to issue the refresh command is a circuit to transmit the refresh command, along with a plurality of bits, to the command interface of the memory device, the plurality of bits to identify at least one bank as a first bank of the plurality of banks to be refreshed in a sequence during the time interval.

6. The memory controller of claim 1 , wherein the circuit to issue the refresh command includes the operation code as a sub-operation code of the refresh command.

7. The memory controller of claim 1 , wherein the circuit to issue an operation code to the memory device is configured to issue a second operation code to the memory device, to place the command interface of the memory device into a loopback mode.

8. The memory controller of claim 7 , including calibration logic to calibrate the command interface of the memory device while the command interface of the memory device is in the loopback mode.

9. The memory controller of claim 1 , wherein the circuit to issue an operation code to the memory device is configured to issue a third operation code specifying an offset voltage calibration operation during which a value representing a receiver voltage offset for a sampler of the memory device is determined and stored in the memory device.

10. A method of operating a memory controller that controls the operation of a memory device, the memory device including a command interface, an on-die termination circuit having a termination resistance, an output driver to transmit data, the output driver having an output drive strength, and a plurality of memory banks, each bank including a plurality of rows of memory cells, the method comprising:
the memory controller issuing a refresh command, wherein the refresh command specifies a refresh operation of the plurality of memory banks of the memory device, the refresh operation to occur during a time interval; and
the memory controller issuing an operation code to the memory device, the operation code specifying a calibration operation, during the time interval, of the termination resistance of the on-die termination circuit and the output drive strength.

11. The method of claim 10 , wherein the operation code is sent to the memory device with the refresh command such that the operation code is issued as part of the refresh command.

12. The method of claim 10 , wherein the refresh command includes a plurality of bits to identify at least one bank as a first bank of the plurality of banks to be refreshed in a sequence in response to the refresh command.

13. The method of claim 12 , wherein the refresh operation is specified as an auto-refresh operation, wherein a row of memory cells is refreshed in the at least one bank identified by the plurality of bits.

14. The method of claim 10 , wherein issuing the refresh command comprises issuing the refresh command along with a plurality of bits to the command interface of the memory device, the plurality of bits to identify at least one bank as a first bank of the plurality of banks to be refreshed in a sequence during the time interval.

15. The method of claim 10 , wherein the refresh command includes the operation code as a sub-operation code of the refresh command.

16. The method of claim 10 , including issuing a second command code to the memory device, to place the command interface of the memory device into a loopback mode.

17. The method of claim 16 , including calibrating the command interface of the memory device while the command interface of the memory device is in the loopback mode.

18. The method of claim 10 , including issuing a third operation code to the memory device specifying an offset voltage calibration operation during which a value representing a receiver voltage offset for a sampler of the memory device is determined and stored in the memory device.

19. A memory controller that controls the operation of a memory device, the memory device including a command interface, an on-die termination circuit having a termination resistance, an output driver to transmit data, the output driver having an output drive strength, and a plurality of memory banks, each bank including a plurality of rows of memory cells, the memory controller comprising:
means for issuing a refresh command to the memory device, wherein the refresh command specifies a refresh operation of the plurality of memory banks of the memory device, the refresh operation to occur during a time interval; and
the means for issuing the refresh command including means for issuing an operation code to the memory device, the operation code specifying a calibration operation, during the time interval, of the termination resistance of the on-die termination circuit of the memory device and the output drive strength of the output driver of the memory device.

20. The memory controller of claim 19 , wherein the operation code is sent to the memory device with the refresh command such that the operation code is issued as part of the refresh command.

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Palmer Robert E
• Poulton John W

Classifications

• G06F13/1636

  using refresh · CPC title

• G11C11/40618

  Refresh operations over multiple banks or interleaving · CPC title

• G06Q10/00

  Administration; Management · CPC title

• G11C11/40615

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G06Q20/00

  Payment architectures, schemes or protocols (apparatus for performing or posting payment transactions G07F7/08, G07F19/00; electronic cash registers G07G1/12) · CPC title