Non-volatile memory with regional and inter-region wear leveling

Patent metadata

Field	Value
Publication number	US-10656844-B2
Application number	US-201715730511-A
Country	US
Kind code	B2
Filing date	Oct 11, 2017
Priority date	Oct 11, 2017
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to map the set of non-volatile memory cells into a plurality of regions, apply a first wear leveling scheme in a first region of the plurality of regions, and apply a second wear leveling scheme between the plurality of regions.

First claim

What is claimed is:

1. A non-volatile storage apparatus, comprising:
a set of non-volatile memory cells; and
one or more control circuits in communication with the set of non-volatile memory cells, the one or more control circuits are configured to map the set of non-volatile memory cells into a plurality of regions, group logical address ranges used by a host into a plurality of groups according to expected access frequency information, assign the plurality of groups to the plurality of regions according to the expected access frequency information, apply a first wear leveling scheme in each of the plurality of regions, remapping according to the first wear leveling scheme triggered by a first number of writes in a first region, the first number selected according to expected endurance characteristics of the first region and remapping according to the first wear leveling scheme triggered by a second number of writes in a second region, the second number selected according to expected endurance characteristics of the second region and apply a second wear leveling scheme between the plurality of regions, the second wear leveling scheme is based on the expected access frequency information, the expected access frequency information is obtained through indicators of expected access frequency sent by the host.

2. The non-volatile storage apparatus of claim 1 wherein the first wear leveling scheme is a deterministic wear leveling scheme.

3. The non-volatile storage apparatus of claim 2 wherein the set of non-volatile memory cells have an expected endurance limit and the first wear leveling scheme is configured to remap received logical data at a rate sufficient to ensure remapping of a sequence of writes to an individual logical address from a first physical address to a second physical address before the expected endurance limit of the first physical address is reached.

4. The non-volatile storage apparatus of claim 1 wherein the one or more control circuits are configured to record wear data for the plurality of regions and the second wear leveling scheme is based on the wear data for the plurality of regions.

5. The non-volatile storage apparatus of claim 4 wherein the second wear leveling scheme assigns logical addresses with low expected access frequency to regions with high wear and assigns logical addresses with high expected access frequency to regions with low wear.

6. The non-volatile storage apparatus of claim 1 wherein the indicators of access frequency sent by the host specify expected access frequency information for one or more NVMe namespaces.

7. The non-volatile storage apparatus of claim 1 wherein the one or more control circuits are configured to obtain additional access frequency information through recording of access frequency experienced over a period of use.

8. The non-volatile storage apparatus of claim 1 wherein the set of non-volatile memory cells comprise phase change memory cells.

9. The non-volatile storage apparatus of claim 1 wherein the set of non-volatile memory cells comprise Resistive Random Access Memory (ReRAM) cells.

10. The non-volatile storage apparatus of claim 1 wherein the set of non-volatile memory cells are formed in a plurality of physical memory levels disposed at different heights above a substrate in a monolithic three-dimensional memory structure, the first region is formed at a first physical memory level, the second region is firmed at a second physical memory level, and the expected endurance characteristics of the first and second regions are obtained from respective heights above the substrate of the first and second physical memory levels.

11. The non-volatile storage apparatus of claim 1 wherein the one or more control circuits are configured to individually apply the first wear leveling scheme to each of the plurality of regions, the first wear leveling scheme is a start gap scheme, region size and rate of remapping of the start gap scheme are sufficient to remap a series of writes to an address prior to reaching an endurance limit, and wherein the second wear leveling scheme is based on recorded wear data for the plurality of regions.

12. A method, comprising:
receiving, from a host, one or more indicators of expected host access patterns associated with host logical addresses;
grouping host logical addresses according to the one or more indicators of expected host access patterns into at least a first group and a second group;
determining expected endurance characteristics of at least a first region of a non-volatile memory located at a first physical level above a substrate and a second region of the non-volatile memory located at a second physical level above the substrate, expected endurance characteristics of the first and second regions determined from the first and second physical levels above the substrate;
initially assigning the first group to the first region of the non-volatile memory and the second group to the second region of the non-volatile memory such that a group with higher expected access frequency is assigned to a region with higher expected endurance;
applying a first instance of a regional wear leveling scheme in the first region of the non-volatile memory in an initial period;
applying a second instance of the regional wear leveling scheme in the second region of the non-volatile memory in the initial period; and
subsequently applying an inter-region wear leveling scheme between the first region of the non-volatile memory and the second region of the non-volatile memory according to recorded access frequency that is recorded in the initial period.

13. The method of claim 12 wherein applying the first instance of the regional wear leveling scheme in the first region includes rotating a mapping of logical addresses to physical addresses of the first region according to a predetermined cyclical pattern.

14. The method of claim 12 wherein applying the inter-region wear leveling scheme includes rotating a mapping of groups of logical addresses to regions of the non-volatile memory according to a predetermined cyclical pattern.

15. The method of claim 12 wherein applying the inter-region wear leveling scheme includes maintaining a first indicator of wear associated with the first region and a second indicator of wear associated with the second region and remapping data according to at least one of the first indicator of wear and the second indicator of wear.

16. The method of claim 12 wherein applying the first instance of the regional wear leveling scheme in the first region includes remapping in response to a first write count in the first region, the first write count selected according to the expected endurance characteristics of the first region and applying the second instance of the regional wear leveling scheme in the second region includes remapping in response to a second write count in the second region, the second write count selected according to the expected endurance characteristics of the second region.

17. The method of claim 12 further comprising: identifying host data access patterns from a plurality of host access commands.

18. A system comprising:
a first region of non-volatile memory located at a first height above a substrate, the first region having high expected endurance based on the first height;
a second region of non-volatile memory located at a second height above the substrate, the second region having low expected endurance;
means for operating a first instance of a mathematical wear leveling scheme in the first region of non-volatile memory,

Assignees

• Western Digital Tech Inc

Inventors

• Helmick Daniel
• Gholamipour Amir
• Mishra Chandan

Classifications

• G06F3/0616 Primary

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/7211

  Wear leveling · CPC title

• G06F3/064

  Management of blocks · CPC title