Memory system and operation method thereof

US10656832B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10656832-B2
Application numberUS-201715617109-A
CountryUS
Kind codeB2
Filing dateJun 8, 2017
Priority dateOct 24, 2016
Publication dateMay 19, 2020
Grant dateMay 19, 2020

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A memory system comprises a memory device including a plurality of memory blocks, a write operation check unit configured to count the number of write operations performed on the respective memory blocks, a write count distribution management module configured to manage a distribution of the memory blocks based on the counted number of the write operations, and a wear leveling module configured to detect hot and cold memory blocks from the plurality of memory blocks based on the counted number of the write operation and the distribution, wherein the wear leveling module manages a history of the hot memory block and swaps the hot memory block with the cold memory block according to the managed history.

First claim

Opening claim text (preview).

What is claimed is: 1. A memory system comprising: a memory device including a plurality of memory blocks; a write operation check circuit configured to count numbers of write operations performed on the plurality of memory blocks, respectively; a write count distribution management hardware module configured to manage a distribution of the plurality of memory blocks based on the counted number of the write operations; and a wear leveling hardware module configured to detect a hot memory block and a cold memory block from the plurality of memory blocks based on the counted numbers of the write operations and the distribution, wherein the hot memory block is included in a first upper range of the distribution, wherein the wear leveling hardware module manages a history of the hot memory block to indicate whether a cold data of the cold memory block is moved to the hot memory block and swaps the hot memory block with the cold memory block when the history of the hot memory block indicates that the hot memory block is unswapped, wherein the wear leveling module checks whether the hot memory block is included in a second upper range higher than the first upper range of the distribution when the history of the hot memory block indicates that the hot memory block is swapped and swaps the checked hot memory block with the cold memory block when the checked hot memory block is included in the second upper range of the distribution. 2. The memory system of claim 1 , wherein the write count distribution management hardware module divides the numbers of the write operations into a plurality of sections, counts numbers of memory blocks included in the plurality of sections, respectively, based on the numbers of write operations, and stores the numbers of memory blocks in a distribution table. 3. The memory system of claim 1 , wherein the wear leveling hardware module manages the history of the hot memory block using flag information denoting whether the hot memory block is swapped. 4. An operation method of a memory system, comprising: managing a distribution of a plurality of memory blocks based on numbers of write operations performed on the plurality of memory blocks, respectively; detecting a hot memory block which is included in a first upper range of the distribution among the plurality of memory block based on the distribution; checking a history of the detected hot memory block; swapping the detected hot memory block with a cold memory block of a cold memory block list when the history of the detected hot memory block is in a first state indicating that the detected hot memory block is unswapped; checking whether the detected hot memory block is included in a second upper range higher than the first upper range of the distribution when the history of the detected hot memory block is in a second state indicating that the detected hot memory block is swapped; swapping the checked hot memory block with the cold memory block of the cold memory block list when the checked hot memory block is included in the second upper range of the distribution; and changing the history of the swapped hot memory block to the second state indicating that a cold data of the cold memory block is moved to the swapped hot memory block. 5. The operation method of the memory system of claim 4 , wherein the detecting of the hot memory block comprises: checking the numbers of write operations performed on a memory block among the plurality of memory blocks; and detecting the memory block as the hot memory block when the memory block is included in the first upper range of the distribution based on the checked number. 6. The operation method of the memory system of claim 5 , wherein the detecting of the memory block as the hot memory block comprises: comparing the checked number with numbers of write operations performed on one or more memory blocks which are included in the first upper range of the distribution, based on a distribution table indicating numbers of memory blocks corresponding to the plurality of sections. 7. The operation method of the memory system of claim 4 , further comprising: detecting an additional cold memory block from the plurality of memory blocks when a number of cold memory blocks of the cold memory block list is equal to or smaller than a reference value, and adding the detected cold memory block to the cold memory block list. 8. The operation method of the memory system of claim 7 , wherein the detecting of the additional cold memory block and the adding of the detected cold memory block to the cold memory block list comprises: checking a number of write operations performed on a first memory block among the plurality of memory blocks; and adding the first memory block to a first list of the cold memory block list when the first memory block is included in a first lower range of the distribution based on the number of write operations performed on the first memory block. 9. The operation method of the memory system of claim 8 , wherein the detecting of the additional cold memory block and the adding of the detected cold memory block to the cold memory block list further comprises: checking whether the first memory block is included in a second lower range higher than the first lower range of the distribution when the first memory block is out of the first lower range of the distribution based on the number of write operations performed on the first memory block; and adding the first memory block to a second list of the cold memory block list when the first memory block is included in the second lower range of the distribution. 10. The operation method of the memory system of claim 9 , wherein, when the first memory block is out of the second lower range of the distribution, the detecting of the cold memory block and the adding of the detected cold memory block to the cold memory block list are repeated on a second memory block among the plurality of memory blocks. 11. The operation method of the memory system of claim 9 , wherein the swapping of the detected hot memory block with the cold memory block of the cold memory block list comprises: checking the cold memory block to be swapped in sequence of the first list and the second list from the cold memory block list. 12. The operation method of the memory system of claim 4 , wherein the managing of the distribution based on the numbers of write operations performed on the plurality of memory blocks comprises: counting the numbers of the write operations performed on the plurality of memory blocks; and dividing the counted numbers of the write operations into a plurality of sections, counting numbers of memory blocks included in the plurality of sections, respectively, based on the counted numbers of the write operations, and storing the counted numbers of memory blocks in a distribution table. 13. An operation method of a memory system, comprising: checking a number of write operations of a memory block, among a plurality of memory blocks; detecting the memory block as a hot memory block when the memory block is included in a first upper range of a distribution of the plurality of memory blocks based on the checked number of write operations; checking a history of the detected hot memory block; swapping the detected hot memory block with a cold memory block of a cold memory block list when the history of the detected hot memory block is in a first state indicating that detected hot memory block is unswapped; checking whether the detected hot memory block is included in a second upper range higher than the first upper range of the distribution when the history of the detected hot

Assignees

Inventors

Classifications

  • Management of blocks · CPC title

  • G06F3/0604Primary

    Improving or facilitating administration, e.g. storage management · CPC title

  • Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

  • Monitoring storage devices or systems · CPC title

  • in block erasable memory, e.g. flash memory · CPC title

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What does patent US10656832B2 cover?
A memory system comprises a memory device including a plurality of memory blocks, a write operation check unit configured to count the number of write operations performed on the respective memory blocks, a write count distribution management module configured to manage a distribution of the memory blocks based on the counted number of the write operations, and a wear leveling module configured…
Who is the assignee on this patent?
Sk Hynix Inc
What technology area does this patent fall under?
Primary CPC classification G06F3/0604. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 19 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).