Processor core power event tracing

Patent metadata

Field	Value
Publication number	US-10656697-B2
Application number	US-201815911577-A
Country	US
Kind code	B2
Filing date	Mar 5, 2018
Priority date	Dec 23, 2014
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.

First claim

What is claimed is:

1. A processor, comprising:
a core;
a power manager to transition the core between a wake state and one or more dormant states; and
a trace unit comprising circuitry to:
detect a first power management event at the processor, wherein the first power management event comprises an entry to a dormant state;
generate a particular trace packet to describe the power management event, wherein the particular trace packet is a particular one of a plurality of different trace packet types generated by the trace unit, and the particular trace packet type comprises a dormant state entry trace packet type;
detect a second power management event at the processor, wherein the second power management event comprises an exit from the dormant state; and
generate another trace packet to describe the second power management event, wherein the second power management event comprises a dormant state exit trace packet type, and fields defined in the dormant state entry trace packet type are different from fields defined in the dormant state exit trace packet type.

2. The processor of claim 1 , wherein the plurality of different trace packet types comprises a plurality of different power management trace packet types.

3. The processor of claim 2 , wherein the plurality of different power management trace packet types further comprise a code execution stop trace packet type and a dormant state request trace packet type.

4. The processor of claim 2 , wherein the plurality of different trace packet types comprises at least one non-power management trace packet type.

5. The processor of claim 1 , wherein at least one of the fields defined in the dormant state exit trace packet type identifies a wake reason associated with an exit to a wake state.

6. The processor of claim 1 , wherein the power management event comprises a clock stoppage.

7. The processor of claim 1 , wherein the power management event comprises entry into a particular one of the one or more dormant states.

8. The processor of claim 7 , wherein the one or more dormant states comprise a plurality of dormant states and the particular trace packet indicates the particular one of the plurality of dormant states.

9. The processor of claim 1 , wherein the power management event comprises a stoppage of code execution by the core.

10. The processor of claim 1 , wherein the trace unit is to buffer the particular trace packet in memory.

11. A method comprising:
transitioning a core of a processor between a wake state and one or more dormant states;
detecting, at a trace unit of the processor, a first power management event at the processor, wherein the first power management event comprises the transitioning from the wake state to the one or more dormant states;
generating a particular trace packet to describe the power management event, wherein the particular trace packet is a particular one of a plurality of different trace packet types generated by the trace unit, and the particular trace packet type comprises a dormant state entry trace packet type;
transitioning the core from the one or more dormant states to the wake state;
detecting a second power management event at the processor, wherein the second power management event comprises the transitioning from the one or more dormant states to the wake state; and
generating another trace packet to describe the second power management event, wherein the second power management event comprises a dormant state exit trace packet type, and fields defined in the dormant state entry trace packet type are different from fields defined in the dormant state exit trace packet type.

12. The method of claim 11 , further comprising:
storing the particular trace packet in a memory;
receiving a request from a software tool to access the particular trace packet from the memory; and
allowing the software to access the particular trace packet.

13. The method of claim 11 , further comprising receiving a request to transition to a particular one of the one or more dormant states, wherein the power management event is based on the request.

14. The method of claim 11 , wherein the plurality of different trace packet types further comprises a code execution stop trace packet type and a dormant state request trace packet type.

15. A system comprising:
memory; and
a processor comprising:
a core;
a power manager to transition the core between a wake state and one or more dormant states; and
a trace unit comprising circuitry to:
detect a first power management event at the processor, wherein the first power management event comprises an entry to a dormant state;
generate a particular trace packet to describe the power management event, wherein the particular trace packet is a particular one of a plurality of different trace packet types generated by the trace unit, and the particular trace packet type comprises a dormant state entry trace packet type;
detect a second power management event at the processor, wherein the second power management event comprises an exit from the dormant state; and
generate another track packet to describe the second power management event, wherein the second power management event comprises a dormant state exit trace packet type, and fields defined in the dormant state entry trace packet type are different from fields defined in the dormant state exit trace packet type.

16. The system of claim 15 , wherein the plurality of different trace packet types comprises a plurality of different power management trace packet types, and the plurality of different power management trace packet types further comprise a code execution stop trace packet type and a dormant state request trace packet type.

17. The system of claim 16 , wherein the plurality of different trace packet types comprises one or more non-power management trace packet types.

18. The system of claim 17 , wherein the trace unit comprises circuitry to detect another event and generate a non-power management trace packet based on the other event.

19. The system of claim 15 , further comprising a software tool to access the particular trace packet from the memory and decode the particular trace packet to identify the power management event.

20. The processor of claim 1 , wherein the trace unit comprises circuitry within the core.

Assignees

• Intel Corp

Inventors

• Kurts Tsvika
• Strong Beeman C
• O'Connor Richard B
• Chynoweth Michael W
• Chabukswar Rajshree A
• Lottem Avner
• Kazachinsky Itamar
• Mishaeli Michael
• Wojciechowski Anthony
• Vasisht Vikas R

Classifications

• G06F2201/86

  Event-based monitoring · CPC title

• G06F11/348

  Circuit details, i.e. tracer hardware · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F11/3024

  where the computing system component is a central processing unit [CPU] · CPC title

• G06F11/3055

  Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available (error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction of the data by redundancy in operations G06F11/14; error detection or correction by redundancy in hardware G06F11/16) · CPC title