Narrow-parallel scan-based device testing

Patent metadata

Field	Value
Publication number	US-10656205-B2
Application number	US-201815886566-A
Country	US
Kind code	B2
Filing date	Feb 1, 2018
Priority date	Feb 1, 2018
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

Embodiments include systems and methods for in-system, scan-based device testing using novel narrow-parallel (NarPar) implementations. Embodiments include a virtual automated test environment (VATE) system that can be disposed within the operating environment of an integrated circuit for which scan-based testing is desired (e.g., a chip under test, or CuT). For example, the VATE system is coupled with a service processor and with the CuT via a novel NarPar interface. A sequence controller can drive a narrow set of parallel scan pins on the CuT via the NarPar interface of the VATE system in accordance with an adapted test sequence having bit vector stimulants and expected responses. Responses of the CuT to the bit vector stimulants can be read out and compared to the expected results for scan-based testing of the chip.

First claim

What is claimed is:

1. A system for scan-based testing of an integrated circuit installed in an operational environment, the system comprising:
a virtual automated test environment (VATE) system comprising:
a sequence controller having a test sequence input to receive a stored test sequence comprising a plurality of bit vector stimulants and expected responses generated by an automated test pattern generator and adapted for a NarPar port set comprising a plurality of parallel scan-in ports and a plurality of scan-out ports that are a subset of parallel scan ports of the integrated circuit;
a narrow-parallel (NarPar) subsystem coupled with the sequence controller and having a NarPar interface to couple with the NarPar port set;
a read-out controller coupled with the NarPar subsystem to receive read-out data from at least one of the plurality of scan-out ports in response to the integrated circuit being set to a NarPar test mode and the NarPar port set being driven by the NarPar subsystem according to the bit vector stimulants; and
a mezzanine board having the VATE system and the integrated circuit disposed thereon.

2. The system of claim 1 , wherein the VATE system further comprises:
a sequence data store, having the test sequence stored thereon.

3. The system of claim 1 , wherein the sequence controller is in communication with a file server separate from the VATE system, and the file server comprises a sequence data store having the test sequence stored thereon.

4. The system of claim 1 , further comprising:
the integrated circuit, coupled with the NarPar subsystem via at least the NarPar interface, the integrated circuit comprising the parallel scan ports, and comprising a mode selector to set the integrated circuit to the NarPar test mode.

5. The system of claim 1 , wherein the VATE system further comprises:
a voting controller coupled with the read-out controller to direct the read-out controller to generate an output stream from the read-out data received from only a selected subset of the plurality of scan-out ports.

6. The system of claim 1 , wherein the VATE system further comprises:
a control port subsystem coupled with the sequence controller and having a control port interface to couple with a control port set of the integrated circuit.

7. The system of claim 6 , wherein the control port subsystem operates to:
detect, while the NarPar port set is being driven by the NarPar subsystem according to the bit vector stimulants, one of the bit vector stimulants as previously associated with a structural adaptation in the integrated circuit; and
communicate, in response to the detecting, a control signal to the integrated circuit directing the structural adaptation in the integrated circuit in temporal accordance with the NarPar port set being driven by the detected one of the bit vector stimulants.

8. The system of claim 6 , wherein the control port set comprises a set of Joint Test Action Group (JTAG) ports.

9. The system of claim 1 , further comprising:
a service processor coupled with the read-out controller via a low-pin-count (LPC) bus.

10. The system of claim 9 , wherein the VATE system further comprises:
a control port subsystem and having a control port interface to couple with a control port set of the integrated circuit, the control port subsystem disposed at least partially in the service processor.

11. A method for scan-based testing of an integrated circuit installed in an operational environment, the method comprising:
setting the integrated circuit to a narrow-parallel (NarPar) test mode;
with a virtual automated test environment (VATE), receiving a stored test sequence comprising a plurality of bit vector stimulants and expected responses generated by an automated test pattern generator and adapted for a NarPar port set comprising a plurality of parallel scan-in ports and a plurality of scan-out ports that are a subset of parallel scan ports of the integrated circuit;
with the VATE, driving the NarPar port set according to the received bit vector stimulants, wherein the VATE and the integrated circuit are disposed on a mezzanine board; and
receiving read-out data from at least one of the plurality of scan-out ports in response to the driving.

12. The method of claim 11 , further comprising:
detecting, during the driving, one or more of a set of bit vector stimulants of the test sequence as previously associated with a structural adaptation in the integrated circuit; and
communicating a control signal to the integrated circuit directing the structural adaptation in the integrated circuit in response to, and in temporal accordance with, the driving.

13. The method of claim 11 , further comprising:
generating a test result as a function of comparing the read-out data with the expected responses of the test sequence.

14. The method of claim 11 , further comprising:
generating an output stream from the read-out data received from only a selected subset of the plurality of scan-out ports as a function of predetermined voting criteria.

15. The method of claim 11 , wherein the receiving comprises receiving the test sequence by a sequence controller from a sequence data store local to the sequence controller.

16. The method of claim 11 , wherein the receiving comprises receiving the test sequence by a sequence controller from a file server remote from the sequence controller.

17. A processor coupled with a memory having instructions stored thereon, which, when executed, cause the processor to perform steps comprising:
setting the integrated circuit to a narrow-parallel (NarPar) test mode;
receiving a stored test sequence comprising a plurality of bit vector stimulants and expected responses generated by an automated test pattern generator and adapted for a NarPar port set comprising a plurality of parallel scan-in ports and a plurality of scan-out ports with each being a differing subset of parallel scan ports of the integrated circuit;
driving the NarPar port set according to the received bit vector stimulants;
receiving read-out data from at least one of the plurality of scan-out ports in response to the driving;
detecting, during the driving, one of a set of bit vector stimulants of the test sequence as previously associated with a structural adaptation in the integrated circuit; and
communicating a control signal to the integrated circuit directing the structural adaptation in the integrated circuit in response to, and in temporal accordance with, the driving.

18. The processor of claim 17 , wherein the steps further comprise:
generating a test result as a function of comparing the read-out data with the expected responses of the test sequence.

Assignees

• Oracle Int Corp

Inventors

• Semmelmeyer Mark
• Vahidsafa Ali
• Turullols Sebastian
• Cooke Scott
• Diraviam Senthilkumar
• Sama Preethi

Classifications

• G01R31/318563 Primary

  Multiple simultaneous testing of subparts · CPC title

• G01R31/318544

  Scanning methods, algorithms and patterns (G01R31/3183 takes precedence) · CPC title

• G01R31/2834

  Automated test systems [ATE]; using microprocessors or computers (G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736) · CPC title

• G01R31/318307 Primary

  computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging · CPC title

• G01R31/318371

  Methodologies therefor, e.g. algorithms, procedures · CPC title