Self testing fault circuit apparatus and method

Patent metadata

Field	Value
Publication number	US-10656199-B2
Application number	US-201715650369-A
Country	US
Kind code	B2
Filing date	Jul 14, 2017
Priority date	Jan 29, 2008
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A process for self testing a fault circuit includes disabling an actuator, performing a self test by creating a simulated fault signal across at least a portion of a half cycle of a first polarity and across at least a portion of a half cycle of a second polarity, and determining whether the self test was successful.

First claim

What is claimed is:

1. A process for self testing a fault circuit comprising:
a) disabling an actuator;
b) performing a self test by creating a simulated fault signal across at least a portion of a half cycle of a first polarity and across at least a portion of a half cycle of a second polarity; and
c) determining whether the self test was successful.

2. The process as in claim 1 , wherein said step of disabling said actuator comprises preventing a signal from reaching said actuator.

3. The process as in claim 2 , wherein said step of disabling said actuator comprises blocking a SCR from receiving a fault signal.

4. The process as in claim 1 , wherein said step of performing a self test comprises creating a current imbalance between a phase and neutral line.

5. The process as in claim 1 , wherein said step of performing a self test comprises:
creating a current imbalance by activating at least one transistor to cause current to flow from at least one electrical conductor configured to be read by at least one fault sensor, wherein said current imbalance is read by said at least one fault sensor.

6. The process as in claim 1 , wherein said step of performing a self test comprises:
a) detecting a zero crossing of an AC line signal;
b) timing a self test to occur during at least a portion of a first half cycle of a first polarity and during at least a portion of a second half cycle of opposite polarity.

7. The process as in claim 6 , further comprising the step of timing a self test during an alternate half cycle of alternating current.

8. The process as in claim 7 , wherein said step of timing a self test during at least one half cycle of alternating current comprises timing a self test during only a portion of said at least one half cycle of alternating current.

9. The process as in claim 1 , further comprising the step of controlling a duration of a self test.

10. The process as in claim 9 , wherein said step of controlling a duration of a self test comprises controlling said duration based upon an amount of power fed into a capacitor.

11. The process as in claim 10 , wherein said step of controlling a duration of a self test comprises controlling a discharge rate of power of said capacitor.

12. The process as in claim 1 , wherein said step of detecting a fault includes receiving a signal from a fault sensor indicating the presence of a fault.

13. The process as in claim 1 , wherein said step of indicating a result of said self test comprises providing a light indication for said self test.

14. The process as in claim 1 , wherein said step of indicating a result of said self test comprises providing an audio indication for said self test.

15. The process as in claim 1 , wherein said step of indicating a result of said self test comprises indicating whether a self test is performed successfully.

16. The process as in claim 1 , wherein said step of indicating a result of said self test comprises indicating whether a set of contacts have tripped.

17. The process as in claim 1 , further comprising the step of determining an overcurrent condition or an overvoltage condition.

18. The process as in claim 1 , further comprising the step of permanently removing the fault circuit from operation by opening a fusable link along at least one of said phase line and said neutral line.

19. The process as in claim 9 , further comprising the step of determining when a fault signal is received to determine whether an external fault is occurring.

20. The process as in claim 19 , further comprising the step of actuating said actuator to remove power to a load side in response to determining that an external fault exists.

21. The process as in claim 9 , further comprising the step activating a transistor to control the duration of a self test.

22. The process as in claim 21 , wherein said step of activating a transistor, comprises turning a transistor on, and wherein the process further includes the step of discharging a capacitor, wherein said step of turning a transistor on, creates a discharge path for said capacitor, to create a shorter test cycle.

23. The process as in claim 22 , wherein after said step of discharging a capacitor is completed, said step of disabling an actuator is completed.

24. The process as in claim 1 , wherein creating a simulated fault signal across at least a portion of a half cycle of a first polarity and across at least a portion of a half cycle of a second polarity comprises:
creating a first simulated fault signal across at least the portion of the half cycle of the first polarity; and
creating a second fault signal across at least the portion of the half cycle of the second polarity.

Assignees

• Leviton Mfg Company
• Leviton Manufacturing Co

Inventors

• Ostrovsky Michael
• Kevelos Adam

Classifications

• G01R31/3277 Primary

  of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches · CPC title

• H02H3/335

  the main function being self testing of the device · CPC title

• G01R31/2884 Primary

  using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title