Wakeup receiver

Patent metadata

Field	Value
Publication number	US-10652823-B2
Application number	US-201815993205-A
Country	US
Kind code	B2
Filing date	May 30, 2018
Priority date	Jun 7, 2017
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

Systems and methods providing a wakeup receiver for latency-critical applications are described herein. An example system includes a wakeup receiver communicatively coupled to a communication channel. The wakeup receiver is configured to monitor an input signal of the communication channel and down-convert the input signal to a DC signal. The system also includes an analog to digital converter (ADC) configured to digitize the DC signal and provide an ADC output. The system further includes a digital baseband (DBB) module configured to determine a received signal strength indication (RSSI) from the signal. The DBB is also configured to, for each packet, determine a respective packet length and compare the RSSI and respective packet length with a two-dimensional template. The DBB is additionally configured to, based on the comparison, determine an interrupt condition and, based on determining the interrupt condition, generate a wakeup signal.

First claim

What is claimed is:

1. A system, comprising:
a wakeup receiver communicatively coupled to a communication channel, wherein the wakeup receiver is configured to:
monitor an input signal of the communication channel, wherein the input signal comprises a plurality of packets, each packet comprising a respective packet length; and
down-convert the input signal to a DC signal;

an analog to digital converter (ADC) configured to digitize the DC signal and provide an ADC output; and
a digital baseband (DBB) module configured to:
apply an automatic gain control (AGC) loop to the ADC output to provide a gain-controlled signal;
determine a received signal strength indication (RSSI) based on the gain-controlled signal;
for each packet, determine the respective packet length;
compare the RSSI and respective packet length with a two-dimensional template;
based on the comparison, determine an interrupt condition; and
based on determining the interrupt condition, generate a wakeup signal.

2. The system of claim 1 , wherein determining the interrupt condition comprises determining that 1) the RSSI is within a pre-defined RSSI range; and 2) the respective packet length is within a pre-defined packet length range.

3. The system of claim 2 , wherein the two-dimensional template comprises a two-dimensional lookup table having a first dimension corresponding to values within the pre-defined RSSI range and a second dimension corresponding to values within the pre-defined packet length range.

4. The system of claim 2 , wherein subsequent to determining the interrupt condition, the DBB is further configured to change a value of the pre-defined RSSI range for a predetermined period of time.

5. The system of claim 1 , further comprising a power management unit (PMU), wherein the PMU is configured to: in response to the wakeup signal, generate a power-on-reset (POR) signal.

6. The system of claim 5 , wherein the PMU comprises a DC-DC converter, a bandgap voltage reference, a plurality of capacitor-less low drop-out voltage regulators, a POR generation circuit, and at least one bias circuit.

7. The system of claim 1 , wherein the wakeup receiver comprises a low-noise amplifier (LNA), an envelope detector (ED), a plurality of baseband amplifiers, and a plurality of clock control circuits.

8. The system of claim 1 , further comprising a 24 MHz Pierce crystal oscillator.

9. The system of claim 1 , wherein each element of the system is coupled to a common substrate.

10. The system of claim 9 , wherein the elements of the system are arranged on the common substrate having an area less than 1.3 mm 2 .

11. A method, comprising:
monitoring, at a wakeup receiver an input signal of a communication channel, wherein the input signal comprises a plurality of packets, each packet comprising a respective packet length;
down-converting the input signal to a DC signal;
digitizing the DC signal with an analog to digital converter (ADC) to provide an ADC output;
applying, with a digital baseband (DBB) module, an automatic gain control (AGC) loop to the ADC output to provide a gain-controlled signal;
determining a received signal strength indication (RSSI) based on the gain-controlled signal;
for each packet, determining the respective packet length;
comparing the RSSI and respective packet length with a two-dimensional template;
based on the comparison, determining an interrupt condition; and
based on determining the interrupt condition, generating a wakeup signal.

12. The method of claim 11 , wherein determining the interrupt condition comprises determining that 1) the RSSI is within a pre-defined RSSI range; and 2) the respective packet length is within a pre-defined packet length range.

13. The method of claim 12 , wherein the two-dimensional template comprises a two-dimensional lookup table having a first dimension corresponding to values within the pre-defined RSSI range and a second dimension corresponding to values within the pre-defined packet length range.

14. The method of claim 12 , further comprising, subsequent to determining the interrupt condition, changing a value of the pre-defined RSSI range for a predetermined period of time.

15. The method of claim 11 , further comprising, with a power management unit (PMU), in response to the wakeup signal, generating a power-on-reset (POR) signal.

16. The method of claim 15 , wherein the PMU comprises a DC-DC converter, a bandgap voltage reference, a plurality of capacitor-less low drop-out voltage regulators, a POR generation circuit, and at least one bias circuit.

17. The method of claim 11 , wherein the wakeup receiver comprises a low-noise amplifier (LNA), an envelope detector (ED), a plurality of baseband amplifiers, and a plurality of clock control circuits.

18. The method of claim 11 , wherein the wakeup receiver further comprise a 24 MHz Pierce crystal oscillator.

19. The method of claim 11 , wherein the wakeup receiver and the DBB are coupled to a common substrate.

20. The method of claim 19 , wherein the wakeup receiver and the DBB are arranged on the common substrate having an area less than 1.3 mm 2 .

21. A digital baseband (DBB) module, comprising:
an automatic gain control (AGC) loop and a processor,
wherein the processor of the DBB module is executable to:
apply the AGC loop to an output of an analog to digital converter (ADC) to provide a gain-controlled signal,
determine a received signal strength indication (RSSI) based on the gain-controlled signal,
for each of a plurality of packets, determine a respective packet length,
compare the RSSI and the respective packet length with a two-dimensional template,
based on the comparison, determine an interrupt condition, and
based on determining the interrupt condition, generate a wakeup signal.

22. A method, comprising:
applying, with a digital baseband (DBB) module, an automatic gain control (AGC) loop to an output of an analog to digital converter (ADC) to provide a gain-controlled signal;
determining a received signal strength indication (RSSI) based on the gain-controlled signal;
for each of a plurality of packets, determining a respective packet length;
comparing the RSSI and the respective packet length with a two-dimensional template;
based on the comparison, determining an interrupt condition; and
based on determining the interrupt condition, generating a wakeup signal.

Assignees

• Panasonic Ip Man Co Ltd
• Stichting Imec Nederland
• Imec Vzw

Inventors

• Ding Ming
• Zhang Peng
• Zhang Yan
• Hirata Akio
• Nagao Akifumi

Classifications

• H04W52/0216

  using a pre-established activity schedule, e.g. traffic indication frame · CPC title

• H03G3/3052

  in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver (H03G3/32, H03G3/34 take precedence) · CPC title

• H04W52/0229 Primary

  where the received signal is a wanted signal · CPC title

• H04W52/245

  taking into account received signal strength · CPC title

• H03M1/1205

  Multiplexed conversion systems · CPC title