Semiconductor device including variable resistance memory device

Patent metadata

Field	Value
Publication number	US-10651236-B2
Application number	US-201916392969-A
Country	US
Kind code	B2
Filing date	Apr 24, 2019
Priority date	Jun 2, 2017
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

A semiconductor device includes a substrate including a memory cell region and a logic region; a variable resistance memory device on the memory cell region; a logic device on the logic region; a first horizontal bit line extending in a horizontal direction on a surface of the substrate on the memory cell region and electrically connected to the variable resistance memory device; a second horizontal bit line extending in a horizontal direction on the surface of the substrate on the logic region and electrically connected to the logic device; and a vertical bit line electrically connected to the first horizontal bit line and the second horizontal bit line and extending perpendicular to the surface of the substrate.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate comprising a memory cell region, a memory cell peripheral region and a logic region;
a variable resistance memory device on the memory cell region;
a first via contact structure extending vertically on the memory cell peripheral region;
a second via contact structure extending vertically on the logic region;
a conductive line extending horizontally and electrically connected to the variable resistance memory device, the first via contact structure and the second via contact structure; and
a plurality of conductive structures electrically connected to the variable resistance memory device and arranged at the memory cell region,
wherein the variable resistance memory device, the first via contact structure and the second via contact structure are arranged between the conductive line and the plurality of conductive structures.

2. The semiconductor device of claim 1 , wherein a width of the first via contact structure is different from a width of the second via contact structure.

3. The semiconductor device of claim 1 , wherein a width of the first via contact structure is smaller than a width of the second via contact structure.

4. The semiconductor device of claim 1 , wherein the plurality of conductive structures comprise a first conductive structure in contact with the variable resistance memory device, and
wherein the variable resistance memory device, the first via contact structure and the second via contact structure are arranged between the conductive line and the first conductive structure.

5. The semiconductor device of claim 1 , wherein the variable resistance memory device, the first via contact structure and the second via contact structure are arranged at a same level.

6. The semiconductor device of claim 1 , wherein a height of the first via contact structure is equal to a height of the second via contact structure.

7. The semiconductor device of claim 1 , wherein a height of the variable resistance memory device is equal to a height of the first via contact structure.

8. The semiconductor device of claim 1 , wherein the conductive line is in contact with the variable resistance memory device, the first via contact structure and the second via contact structure.

9. The semiconductor device of claim 1 , wherein the conductive line is in contact with an upper surface of the variable resistance memory device.

10. The semiconductor device of claim 1 , wherein the variable resistance memory device comprises a magnetic tunnel junction device.

11. A semiconductor device comprising:
a substrate comprising a memory cell region, a memory cell peripheral region and a logic region;
a variable resistance memory device on the memory cell region;
a first via contact structure extending vertically on the memory cell peripheral region;
a second via contact structure extending vertically on the logic region; and
a conductive line extending horizontally on the memory cell region, on the memory cell peripheral region and on the logic region,
wherein the conductive line is configured to be electrically connected to the variable resistance memory device, the first via contact structure and the second via contact structure.

12. The semiconductor device of claim 11 , wherein a width of the first via contact structure is different from a width of the second via contact structure.

13. The semiconductor device of claim 11 , wherein a width of the first via contact structure is smaller than a width of the second via contact structure.

14. The semiconductor device of claim 11 , wherein the conductive line is in contact with the variable resistance memory device, the first via contact structure and the second via contact structure.

15. The semiconductor device of claim 11 , wherein the conductive line is in contact with an upper surface of the variable resistance memory device.

16. The semiconductor device of claim 11 , further comprising:
a first insulating layer arranged at a same level as the variable resistance memory device; and
a second insulating layer disposed under the variable resistance memory device,
wherein the first insulating layer and the second insulating layer comprise different materials.

17. The semiconductor device of claim 16 , wherein a gap fill characteristic of the first insulating layer is better than a gap fill characteristic of the second insulating layer.

18. The semiconductor device of claim 16 , wherein a dielectric constant of the first insulating layer is different from a dielectric constant of the second insulating layer.

19. The semiconductor device of claim 16 , wherein a dielectric constant of the first insulating layer is greater than a dielectric constant of the second insulating layer.

20. The semiconductor device of claim 11 , wherein the variable resistance memory device comprises a magnetic tunnel junction device.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Kil-Ho
• Song Yoon-Jong
• Koh Gwan-Hyeob

Classifications

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1655

  Bit-line or column circuits · CPC title

• H01L43/02

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic