Thin film transistor and preparation method thereof, array substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-10651211-B2
Application number	US-201615309949-A
Country	US
Kind code	B2
Filing date	Apr 8, 2016
Priority date	Jun 15, 2015
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

A thin film transistor and a preparation method thereof, an array substrate and a display apparatus are provided. The preparation method includes an operation of forming a low temperature poly silicon active layer; a substrate has a first region and a second region; and the step includes: forming a buffer layer on the first region and the second region of the substrate, the buffer layer having a thickness at a portion corresponding to the first region greater than that at a portion corresponding to the second region; or, forming the buffer layer on the first region of the substrate; forming an amorphous silicon layer on the buffer layer; performing laser crystallization processing on the amorphous silicon layer so as to convert the amorphous silicon layer into a poly silicon layer; and removing the poly silicon layer on the second region, and forming the low temperature poly silicon active layer on the first region.

First claim

What is claimed is:

1. A preparation method of a thin film transistor, comprising: an operation of forming a low temperature poly silicon active layer on a substrate, wherein the substrate comprising a first region and a second region; the first region corresponds to a pattern of the low temperature poly silicon active layer to be formed, and the second region is at least positioned on both opposite sides of the low temperature poly silicon active layer to be formed, the low temperature poly silicon active layer comprises a predetermined region, a source electrode contact region and a drain electrode contact region, and the predetermined region corresponds to a region opposite to a source electrode and a drain electrode which are to be formed, and the source electrode contact region and the drain electrode contact region are respectively positioned on two opposite sides in the first region, which are close to the second region, and
the operation of forming the low temperature poly silicon active layer on the substrate includes:
forming a buffer layer on the first region and the second region of the substrate by a first patterning process, the buffer layer having a thickness at a portion corresponding to the first region greater than that at a portion corresponding to the second region;
forming an amorphous silicon layer on the buffer layer;
performing laser crystallization processing on the amorphous silicon layer so as to convert the amorphous silicon layer into a poly silicon layer;
removing the poly silicon layer on the second region by a second patterning process, and forming the low temperature poly silicon active layer on the first region; and
shielding a region in the predetermined region except a first portion region and a second portion region by a masking process; carrying out ion doping in the source electrode contact region and the first portion region of the predetermined region, which is close to the source electrode contact region, so as to form a first doped region; and carrying out ion doping in the drain electrode contact region and the second portion region of the predetermined region, which is close to the drain electrode contact region, so as to form a second doped region;

wherein the masking process and the first patterning process adopt a same mask; and/or, the masking process and the second patterning process adopt a same mask;
wherein the operation of removing the poly silicon layer on the second region by the second patterning process and forming the low temperature poly silicon active layer on the first region comprises: forming photoresist on the formed poly silicon layer; carrying out exposure and development with the mask on the substrate on which the photoresist is formed so as to form a photoresist fully-reserved region and a photoresist fully-removed region, wherein the photoresist fully-reserved region corresponds to the first region, and the photoresist fully-removed region corresponds to the second region; and removing the poly silicon layer exposed out of the photoresist fully-removed region by an etching process, so as to form a pattern of the low temperature poly silicon active layer; and
wherein the operation of shielding the region in the predetermined region except the first portion region and the second portion region of the predetermined region by the masking process comprises: carrying out for a first-time exposure and development with the mask on the substrate on which the photoresist fully-reserved region is formed so as to form a first photoresist fully-reserved region and a first photoresist fully-removed region, wherein a fully-transmittance region of the mask corresponds to the first photoresist fully-removed region, and the first photoresist fully-removed region corresponds to the first doped region to be formed or the second doped region to be formed; and a fully-non-transmittance region of the mask corresponds to the formed first photoresist fully-reserved region, and the first photoresist fully-reserved region corresponds to a remaining region of the photoresist fully-reserved region; and carrying out for a second-time exposure and development with the mask on the substrate on which the first photoresist fully-reserved region is formed so as to form a second photoresist fully-reserved region and a second photoresist fully-removed region, wherein the fully-transmittance region of the mask corresponds to the second photoresist fully-removed region, and the second photoresist fully-removed region corresponds to the second doped region to be formed or the first doped region to be formed; and the fully-non-transmittance region of the mask corresponds to the formed second photoresist fully-reserved region, and the second photoresist fully-reserved region corresponds to a remaining region of the first photoresist fully-reserved region.

2. The preparation method according to claim 1 , wherein the operation of forming the buffer layer on the first region and the second region of the substrate by the first patterning process, the buffer layer having the thickness at the portion corresponding to the first region greater than that at the portion corresponding to the second region, includes:
sequentially forming a buffer layer thin film and photoresist on the substrate;
carrying out exposure and development with the mask on the substrate on which the photoresist is formed so as to form the photoresist fully-reserved region and the photoresist fully-removed region, wherein the photoresist fully-reserved region corresponds to the first region and the photoresist fully-removed region corresponds to the second region;
rendering a thickness of a portion of the buffer layer thin film, which is exposed out of the photoresist fully-removed region, to be smaller than that of a portion of the buffer layer thin film, which is covered by the photoresist fully-reserved region, by a thinning process; and
removing the photoresist fully-reserved region covered on the buffer layer thin film corresponding to the first region, by an ashing process.

3. The preparation method according to claim 1 , wherein a width of the first doped region along a turning-on direction is from 1 μm to 2 μm; and/or, a width of the second doped region along the turning-on direction is from 1 μm to 2 μm,
wherein the turning-on direction is a direction pointing to the drain electrode contact region from the source electrode contact region.

4. The preparation method according to claim 1 , further comprising: before converting the amorphous silicon layer into the poly silicon layer,
carrying out a dehydrogenation process on the formed amorphous silicon layer.

5. The preparation method according to claim 1 , further comprising: after forming the low temperature poly silicon active layer on the first region,
sequentially forming a gate insulating layer, a pattern layer including a gate electrode, an interlayer insulating layer, and a pattern layer including a source electrode and a drain electrode, on the formed low temperature poly silicon active layer,
wherein the source electrode and the drain electrode are in contact with the low temperature poly silicon active layer respectively through a first via hole and a second via hole which run through the interlayer insulating layer and the gate insulating layer.

6. The preparation method according to claim 1 , wherein the buffer layer is made of any one of materials: silicon oxide, silicon nitride or silicon oxynitride.

7. The preparation method according to claim 1 , wherein the second region is positioned around the first region.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Zuqiang
• Liu Chien Hung

Classifications

• H01L27/1222

  Electricity · mapped topic

• H01L27/1281 Primary

  Electricity · mapped topic

• H01L29/78675

  Electricity · mapped topic

• H01L29/786

  Electricity · mapped topic

• H01L27/1218

  Electricity · mapped topic