Semiconductor device and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-10651209-B2
Application number	US-201716072910-A
Country	US
Kind code	B2
Filing date	Jan 16, 2017
Priority date	Jan 27, 2016
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

A semiconductor device includes: a first thin film transistor (101) including a crystalline silicon semiconductor layer (13); and a second thin film transistor (102) including an oxide semiconductor layer (23). First source/drain electrodes (31), (33) of the first thin film transistor (101) are provided on the crystalline silicon semiconductor layer via a first interlevel dielectric layer (L1); a second source electrode (25S) of the second thin film transistor (102) is electrically connected to a line (35) which is made of the same conductive film as the first source/drain electrodes; the line (35) is provided on the second source electrode (25S) via a second interlevel dielectric layer (L2), and is in contact with the second source electrode (25S) within a second contact hole including an opening made in the second interlevel dielectric layer (L2); the second source electrode has a multilayer structure including a main layer (25m) and an upper layer (25u) disposed on the main layer such that, under the opening in the second interlevel dielectric layer, the upper layer (25u) has a first aperture and the main layer (25m) has a second aperture (p2) or recess, the second aperture (p2) or recess being larger than the first aperture (p1) as viewed from the normal direction of the substrate.

First claim

The invention claimed is:

1. A semiconductor device comprising: a substrate; and a first thin film transistor and a second thin film transistor supported on the substrate, wherein,
the first thin film transistor includes a first gate electrode, a crystalline silicon semiconductor layer, a first gate dielectric layer interposed between the first gate electrode and the crystalline silicon semiconductor layer, and a first source electrode and a first drain electrode electrically connected to the crystalline silicon semiconductor layer;
the second thin film transistor includes a second gate electrode, an oxide semiconductor layer, a second gate dielectric layer interposed between the second gate electrode and the oxide semiconductor layer, and a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer;
the first source electrode and the first drain electrode are provided on the crystalline silicon semiconductor layer via a first interlevel dielectric layer, and are in contact with the crystalline silicon semiconductor layer respectively within a first source contact hole and a first drain contact hole made in the first interlevel dielectric layer;
the second source electrode is electrically connected to a line which is made of a same conductive film as the first source electrode and the first drain electrode;
the line is provided on the second source electrode via a second interlevel dielectric layer, and is in contact with the second source electrode within a second contact hole, the second contact hole including an opening made in the second interlevel dielectric layer; and
the second source electrode has a multilayer structure including a main layer and an upper layer disposed on the main layer, wherein under the opening in the second interlevel dielectric layer the upper layer has a first aperture and the main layer has a second aperture or a recess, the second aperture or recess being larger than the first aperture as viewed from a normal direction of the substrate.

2. The semiconductor device of claim 1 , wherein a side face of the second aperture or recess of the main layer is not in contact with the line.

3. The semiconductor device of claim 1 or 2 , wherein the line is in contact with a side face of the first aperture of the upper layer.

4. The semiconductor device of claim 3 , further including a conductive layer made of the conductive film, the conductive layer being located in the second aperture or recess and being electrically isolated from the line.

5. The semiconductor device of claim 1 , wherein,
the main layer has the recess, such that at least a portion of a bottom face of the recess is exposed through the first aperture of the upper layer; and
the line is in contact with the bottom face of the recess within the second contact hole.

6. The semiconductor device of claim 1 , wherein,
the second source electrode further includes a lower layer located on the substrate side of the main layer;
the main layer has the second aperture, such that a portion of the lower layer is exposed through the second aperture; and
the line is in contact with the exposed portion of the lower layer within the second contact hole.

7. The semiconductor device of claim 5 , wherein a side face of the first aperture of the upper layer is not in contact with the line.

8. The semiconductor device of claim 1 , wherein the upper layer is made of a material having a smaller etching rate with respect to hydrofluoric acid than that of the main layer.

9. The semiconductor device of claim 1 , wherein the main layer contains Al or Cu.

10. The semiconductor device of claim 1 , wherein the upper layer contains Ti or Mo.

11. The semiconductor device of claim 1 , wherein,
the first thin film transistor has a top gate structure, and the second thin film transistor has a bottom gate structure, the first gate electrode and the second gate electrode being provided in same layer; and
the first interlevel dielectric layer includes the first gate dielectric layer, the second gate dielectric layer, and the second interlevel dielectric layer.

12. The semiconductor device of claim 1 , wherein the oxide semiconductor layer comprises an In—Ga—Zn—O based semiconductor.

13. The semiconductor device of claim 12 , wherein the In—Ga—Zn—O based semiconductor includes a crystalline portion.

14. The semiconductor device of claim 1 , wherein the oxide semiconductor layer has a multilayer structure.

15. The semiconductor device of claim 1 , wherein the second thin film transistor is of a channel-etch type.

16. A method of producing a semiconductor device including, on a substrate: a first thin film transistor having an active layer which is a crystalline silicon semiconductor layer; and a second thin film transistor having an active layer which is an oxide semiconductor layer, the first thin film transistor being disposed in a first TFT forming region and the second thin film transistor being disposed in a second TFT forming region, the method comprising:
(A) a step of providing a substrate, including: in the first TFT forming region, the crystalline silicon semiconductor layer and a first interlevel dielectric layer covering the crystalline silicon semiconductor layer; and, in the second TFT forming region, a source electrode and a drain electrode of the second thin film transistor, and a second interlevel dielectric layer covering the source electrode and the drain electrode, the source electrode and the drain electrode having a multilayer structure including a main layer and an upper layer on the main layer, the upper layer having a smaller etching rate with respect to hydrofluoric acid than that of the main layer;
(B) a step of making a first source contact hole and a first drain contact hole in the first interlevel dielectric layer, the first source contact hole and the first drain contact hole reaching the crystalline silicon semiconductor layer, and an opening in the second interlevel dielectric layer, the opening reaching the source electrode;
(C) a step of cleaning a surface of the crystalline silicon semiconductor layer exposed through the first source contact hole and the first drain contact hole with a cleaning agent containing hydrofluoric acid, wherein, as a result of the upper layer and the main layer of the source electrode being etched with the cleaning agent, under the opening in the second interlevel dielectric layer, a first aperture is made in the upper layer and a second aperture or a recess is made in the main layer, thus forming a second contact hole which includes the opening, the first aperture, and the second aperture or recess; and
(D) a step of forming, on the second interlevel dielectric layer and in the second contact hole, a line which is in contact with the source electrode within the second contact hole.

17. The method of producing a semiconductor device of claim 16 , wherein, as viewed from the normal direction of the substrate, the second aperture or recess is larger than the first aperture.

18. The method of producing a semiconductor device of claim 16 , wherein the oxide semiconductor layer comprises an In—Ga—Zn—O based semiconductor.

19. The semiconductor device of claim 1 , further including a driving line for an in-cell touch-screen panel, the driving line for an in-cell touch-screen panel being made of a same conductor film as the line.

20. An in-cell touch-screen type display device comprising the semiconductor device of claim 19 .

Assignees

• Sharp Kk

Inventors

• Saitoh Takao
• Kanzaki Yohsuke
• Nakazawa Makoto
• ITO Kazuatsu
• Kaneko Seiji

Classifications

• G06F2203/04103

  Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices · CPC title

• H01L27/127

  Electricity · mapped topic

• H01L27/1225

  Electricity · mapped topic

• H01L21/76877

  Electricity · mapped topic

• G06F3/044

  by capacitive means · CPC title