Wrap-around contact on FinFET

Patent metadata

Field	Value
Publication number	US-10651091-B2
Application number	US-201916390874-A
Country	US
Kind code	B2
Filing date	Apr 22, 2019
Priority date	Apr 21, 2014
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

First claim

What is claimed is:

1. A structure comprising:
a fin structure on a substrate, the fin structure comprising an epitaxial region, the epitaxial region having an upper surface and an under-surface;
a silicide region at the upper surface of the epitaxial region;
a first contact over the epitaxial region, the first contact comprising a first metal layer directly contacting the silicide region; and
a metal-insulator-semiconductor (MIS) contact on the under-surface of the epitaxial region.

2. The structure of claim 1 , wherein the MIS contact comprises:
a dielectric layer contacting the under-surface of the epitaxial region; and
a barrier layer contacting the dielectric layer.

3. The structure of claim 2 , wherein the dielectric layer comprises a metal oxide.

4. The structure of claim 2 , wherein the dielectric layer does not extend over the upper surface of the epitaxial region.

5. The structure of claim 2 , wherein the barrier layer is further disposed over the first contact.

6. The structure of claim 5 , wherein the barrier layer separates the dielectric layer from a conductive material, and wherein the barrier layer further separates the first contact from the conductive material.

7. The structure of claim 2 , wherein the barrier layer comprises a metal nitride.

8. The structure of claim 1 further comprising a etch stop layer between the MIS contact and a portion of the fin structure, the portion of the fin structure under the epitaxial region.

9. The structure of claim 8 , wherein the etch stop layer comprises a first sub-layer and a second sub-layer over the first sub-layer, wherein the first sub-layer and the second sub-layer have different material compositions.

10. A semiconductor device comprising:
a semiconductor fin;
a gate structure over and extending along sidewalls of the semiconductor fin, the gate structure comprising a gate dielectric and a gate electrode;
a source/drain structure adjacent the gate structure;
a dielectric layer on an underside of the source/drain structure;
a metal-semiconductor compound layer disposed at a top surface of the source/drain structure, wherein the metal-semiconductor compound layer comprises a compound of a metal and a semiconductor, and wherein the dielectric layer contacts a bottom surface of the metal-semiconductor compound layer;
a first metal layer on the metal-semiconductor compound layer;
a conformal barrier layer on the first metal layer and the dielectric layer; and
a second metal layer on the conformal barrier layer.

11. The semiconductor device of claim 10 , the second metal layer extends along sidewalls of the dielectric layer.

12. The semiconductor device of claim 10 , wherein the dielectric layer comprises an oxide of a metal, wherein the conformal barrier layer comprises a nitride of the metal, and wherein the first metal layer comprises the metal.

13. The semiconductor device of claim 12 , wherein the metal-semiconductor compound layer comprises a semiconductor compound of the metal.

14. The semiconductor device of claim 12 , wherein the dielectric layer comprises titanium oxide, wherein the conformal barrier layer comprises titanium nitride, and wherein the first metal layer comprises titanium.

15. The semiconductor device of claim 14 , wherein the metal-semiconductor compound layer comprises titanium, silicon, and germanium.

16. A semiconductor device comprising:
a first fin extending from a substrate;
a first epitaxial region over the first fin;
a first metal layer over a top surface of the first epitaxial region, the first metal layer electrically connected to the first epitaxial region;
a dielectric layer physically contacting an under surface of the first epitaxial region;
a second metal layer over the first metal layer and the dielectric layer, wherein the second metal layer further extends from above the first metal layer to below the first metal layer; and
a conformal barrier layer physically separating the second metal layer from the dielectric layer, the conformal barrier layer further physically separating the first metal layer from the second metal layer.

17. The semiconductor device of claim 16 , further comprising a silicide region at the top surface of the first epitaxial region, wherein the first metal layer contacts the silicide region.

18. The semiconductor device of claim 16 , wherein the dielectric layer has a thickness in the range of 0.5 nm and 8 nm.

19. The semiconductor device of claim 16 , wherein the first metal layer has a thickness in the range of 2 nm and 12 nm.

20. The semiconductor device of claim 16 , wherein the conformal barrier layer has a thickness in a range of 1 nm and 4 nm.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Sung-Li
• Chen Neng-Kuo
• Shih Ding-Kang
• Chang Meng-Chun
• Lin Yi-An
• Huang Gin-Chen
• Hsu Chen-Feng
• Lin Hau-Yu
• Ko Chih-Hsin
• Sun Sey-Ping
• Wann Clement Hsingjen

Classifications

• H01L21/823475

  Electricity · mapped topic

• H01L29/7854

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic

• H01L21/823418

  Electricity · mapped topic

• H01L2029/7858

  Electricity · mapped topic