Secure memory systems

US10650169B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10650169-B2
Application numberUS-201515573081-A
CountryUS
Kind codeB2
Filing dateSep 14, 2015
Priority dateSep 14, 2015
Publication dateMay 12, 2020
Grant dateMay 12, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

There is provided an example memory system comprising a plurality of memory modules, each memory module comprising a persistent memory to store root key information and encrypted primary data; a volatile memory to store a working key for encrypting data, the encrypted primary data stored in the persistent memory being encrypted using the working key; and a control unit to provide load and store access to the primary data. The memory system further comprises a working key recovery mechanism to retrieve first root key information from a first module and second root key information from a second module; and compute the working key for a given module based on the retrieved first root key information and the retrieved second root key information.

First claim

Opening claim text (preview).

We claim: 1. A memory system comprising: a plurality of memory modules, wherein a first memory module of the plurality of memory modules comprises: a solid-state non-volatile memory to store root key information and encrypted primary data, the encrypted primary data being based on encryption of primary data using a working key, the root key information comprising a masked root key produced by combining a root key and a mask value, wherein the mask value comprises at least two mask shares distributed among the plurality of memory modules, a volatile memory to store the working key for decrypting the encrypted primary data and encrypting the primary data, a control circuit to load the primary data and store the encrypted primary data; and a working key recovery mechanism comprising a hardware processor to: retrieve a first mask share of the mask value from a second memory module of the plurality of memory modules, and a second mask share of the mask value from a third memory module of the plurality of memory modules, compute the mask value using the first mask share of the mask value and the second mask share of the mask value, compute the root key using the masked root key and the computed mask value, and compute the working key from the computed root key. 2. The memory system of claim 1 , wherein the working key recovery mechanism is implemented by at least one of the plurality of memory modules. 3. The memory system of claim 1 , further comprising a module manager in communication with each of the plurality of memory modules, wherein the working key recovery mechanism comprises a set of instructions for execution by a processor of the module manager. 4. The memory system of claim 1 , wherein the root key associated with the first memory module is also associated with at least one other memory module of the plurality of memory modules, or the mask value associated with the first memory module is also associated with at least one other memory module of the plurality of memory modules. 5. The memory system of claim 1 , wherein the root key is a first root key, wherein the first memory module is associated with the first root key, and the second memory module is associated with a second, different root key, and wherein the masked root key stored in the solid-state non-volatile memory of the first memory module is a first masked root key derived from the first root key, and a solid-state non-volatile memory of the second memory module is to store a second masked root key derived from the second root key. 6. The memory system of claim 1 , wherein the hardware processor of the working key recovery mechanism is to compute the working key for the first memory module using one of a secret sharing scheme, or a threshold cryptography scheme. 7. The memory system of claim 1 , wherein the control circuit is to load the primary data via a memory bus to at least one processor. 8. The memory system of claim 1 , wherein the first mask share of the mask value is from a solid-state non-volatile memory of the second memory module, and the second mask share of the mask value is from a solid-state non-volatile memory of the third memory module. 9. The memory system of claim 8 , wherein the hardware processor of the working key recovery mechanism is to further: retrieve a third share of the mask value from the solid-state non-volatile memory of the first memory module, and compute the mask value based further on the third share of the mask value. 10. The memory system of claim 1 , wherein the hardware processor of the working key recovery mechanism is to further send the computed mask value to the first memory module, and wherein the control circuit of the first memory module is to decrypt the encrypted primary data using the computed mask value received from the working key recovery mechanism. 11. The memory system of claim 1 , wherein the masked root key is based on one of: an exclusive or (XOR) of the root key and the mask value, an addition of the root key and the mask value, a multiplication of the root key and the mask value, a cryptographic operation of the root key and the mask value, or a hashing process of the root key and the mask value. 12. A method for securing a memory system comprising a plurality of memory modules, each memory module of the plurality of memory modules comprising a solid-state non-volatile memory and a volatile memory, the method comprising: retrieving different mask shares of a mask value from respective solid-state non-volatile memories of at least two memory modules of the plurality of memory modules, wherein the mask value comprises at least two mask shares distributed among the plurality of memory modules; computing the mask value for a given memory module of the plurality of memory modules using the retrieved different mask shares of the mask value, wherein the given memory module is different from the at least two memory modules; computing a root key for the given memory module based on the computed mask value and a masked root key, wherein the masked root key is produced by combining the root key and the mask value; computing a working key for the given memory module based on the computed root key; storing the computed working key for the given memory module in the volatile memory of the given memory module, the computed working key for encrypting primary data, and decrypting the encrypted primary data; loading the primary data; and storing the encrypted primary data, in the solid-state non-volatile memory of the given memory module. 13. The method of claim 12 , comprising: generating a new mask value associated with the given memory module; dividing the generated new mask value into at least two new mask shares; and updating root key information stored by the given memory module by replacing a mask share stored in the solid-state non-volatile memory of the given memory module with one of the new mask shares, and replacing the masked root key stored in the solid-state non-volatile memory of the given memory module with a new masked root key, the new masked root key being derived from the one of the new mask shares and the root key associated with the given memory module. 14. The method of claim 12 , wherein the root key associated with the given memory module is a highest-level key of a key hierarchy associated with the given memory module, the key hierarchy for use in accessing data stored in the solid-state non-volatile memory of the given memory module. 15. The method of claim 12 , wherein the mask value is computed further based on another mask share of the mask value retrieved from the solid-state non-volatile memory of the given memory module.

Assignees

Inventors

Classifications

  • using tree structure or hierarchical structure · CPC title

  • Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage · CPC title

  • Providing cryptographic facilities or services · CPC title

  • G06F21/79Primary

    in semiconductor storage media, e.g. directly-addressable memories · CPC title

  • Key transport or distribution, i.e. key establishment techniques where one party creates or otherwise obtains a secret value, and securely transfers it to the other(s) (network architectures or network communication protocols for key distribution in a packet data network H04L63/062) · CPC title

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What does patent US10650169B2 cover?
There is provided an example memory system comprising a plurality of memory modules, each memory module comprising a persistent memory to store root key information and encrypted primary data; a volatile memory to store a working key for encrypting data, the encrypted primary data stored in the persistent memory being encrypted using the working key; and a control unit to provide load and store…
Who is the assignee on this patent?
Hewlett Packard Entpr Dev Lp
What technology area does this patent fall under?
Primary CPC classification G06F21/79. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 12 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).