Deferred inter-processor interrupts

Patent metadata

Field	Value
Publication number	US-10649935-B2
Application number	US-201816195478-A
Country	US
Kind code	B2
Filing date	Nov 19, 2018
Priority date	Jan 15, 2013
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.

First claim

What is claimed is:

1. A data processing system comprising:
a first processor;
a second processor; and
an interrupt controller coupled to the first processor and to the second processor, the interrupt controller having a delayed inter-processor interrupt (IPI) register that is configured, when set by the first processor, to indicate that the first processor has requested a delayed IPI, and the interrupt controller having a timer to determine when a predetermined time period expires, the predetermined time period starting in response to the interrupt controller receiving the delayed IPI, and the interrupt controller being configured to wake up the second processor and to assign a runnable thread to the second processor to process the runnable thread when the timer having the predetermined time period expires, wherein the interrupt controller is coupled to one or more devices or sources to receive interrupts for processing, wherein cancellation of the delayed IPI is in response to the first processor becoming available to process the runnable thread before the timer having the predetermined time period expires.

2. The system as in claim 1 wherein the interrupt controller comprises a cancel indicator that is configured to receive a cancel signal from the first processor to cancel the delayed IPI, and wherein when the predetermined time period of the timer expires and the cancel signal has not been received, the interrupt controller wakes up the second processor and assigns the runnable thread to the second processor for processing.

3. The system as in claim 1 wherein an interrupt handler in the first processor cannot be interrupted but a thread in either of the first processor or the second processor can be interrupted.

4. The system as in claim 1 wherein a scheduler, executing on the first processor, requests the delayed IPI.

5. The system as in claim 1 wherein the delayed IPI specifies the predetermined time period to be used by the timer to set a time out period.

6. The system as in claim 1 wherein the timer provides the predetermined time period to be used by the timer.

7. The system as in claim 1 wherein the first processor processes the runnable thread after cancelling the delayed IPI.

8. The system as in claim 1 wherein the data processing system has no priority scheme for interrupts.

Assignees

• Apple Inc

Inventors

• Kumar Derek R
• De Cesare Joshua Phillips

Classifications

• G06F1/3293

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title

• G06F9/4418

  Suspend and resume; Hibernate and awake · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• Y02D10/14

  Cross-Sectional Technologies · mapped topic

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title