Memory access system

Patent metadata

Field	Value
Publication number	US-10649663-B2
Application number	US-201715665075-A
Country	US
Kind code	B2
Filing date	Jul 31, 2017
Priority date	Jul 31, 2017
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

A method and system for accessing a memory for a data processing system. The method comprises sending a read request for a plurality of locations in the memory to read the plurality of locations in parallel based on an upper bound for reading the memory. The upper bound for a number of locations is based on a group of constraints for the memory. The method receives a summed value of a plurality of memory values in the plurality of locations in the memory.

First claim

What is claimed is:

1. A method for accessing a memory for a data processing system, the method comprising:
designating, by a controller, a plurality of locations in the memory as a base portion of locations;
sending, by a controller, a read request to read the plurality of locations in parallel within an upper bound that indicates a maximum number of locations that may be read in parallel from the memory according to a group of constraints for the memory;
receiving from the memory, by the controller, a summed value of respective binary values in the plurality of locations in the memory according to a summation function in the memory;
if the summed value received from the memory is zero, cease using those locations to read the memory;
if the summed value received from the memory is non-zero and more than one location is present, dividing, by the controller, the base portion into a plurality of smaller portions of locations;
designating, by the controller, each smaller portion of locations as new respective base portions;
sending, by the controller, read requests for the locations in each new base portion; and
iteratively repeating, by the controller, the steps of dividing base portions with non-zero summed values and more than one location into smaller respective base portions and sending read requests for locations in the new base portions, until there are no unread base portions in the memory with non-zero sums and more than one location.

2. The method of claim 1 further comprising:
identifying a sampling pattern for sampling the locations in the memory, wherein the sampling pattern is used to identify the plurality of locations for the read request.

3. The method of claim 2 further comprising:
repeating the steps of identifying the sampling pattern for sampling the locations in the memory, sending the read request for the plurality of locations in a memory device to read the plurality of locations in parallel based on the upper bound, and receiving the summed value of the plurality of memory values in the plurality of locations in the memory using the sampling pattern to obtain summed values.

4. The method of claim 3 further comprising:
reconstructing memory values in the memory using the summed values via a simplex or interior-point method of linear programming.

5. The method of claim 3 further comprising:
creating the sampling pattern taking into account factors for reconstructing memory values and the upper bound.

6. The method of claim 1 further comprising:
reconstructing the memory is constructed from the locations with non-zero summed values.

7. The method of claim 1 , wherein a constraint is based on at least one of an amount of power, a voltage, a current, or a physical limit on parallel reads for a memory device.

8. The method of claim 1 , wherein the memory is selected from one of a cross point memory, a cross bar memory, a dynamic random access memory, an optical memory, and a quantum memory.

9. A memory system comprising:
a memory comprising a summation function that allows for parallel input of addresses for locations in the memory; and
a controller configured to:
designate a plurality of locations in the memory as a base portion of locations;
send a read request to read the plurality of locations in parallel within an upper bound that indicates a maximum number of locations that may be read in parallel from the memory according to a group of constraints for the memory;
receive a summed value of respective binary memory values in the plurality of locations in the memory according to the summation function;
if the summed value received from the memory is zero, cease using those locations to read the memory;
if the summed value received from the memory is non-zero and more than one location is present, divide the base portion into a plurality of smaller portions of locations;
designating each smaller portion of locations as new respective base portions;
sending read requests for the locations in each new base portion; and
iteratively repeat the steps of dividing base portions with non-zero summed values and more than one location into smaller respective base portions and sending read requests for locations in the new base portions, until there are no unread base portions in the memory with non-zero sums and more than one location.

10. The memory system of claim 9 , wherein the controller identifies a sampling pattern for sampling the plurality of locations in the memory, wherein the sampling pattern is used to identify the plurality of locations for the read request.

11. The memory system of claim 10 , wherein the controller repeats identifying the sampling pattern for sampling locations in the memory; sending the read request for the plurality of locations in a memory device to read the plurality of locations in parallel based on the upper bound for reading the memory; and receiving the summed value of the plurality of memory values in the plurality of locations in the memory using the sampling pattern to obtain summed values.

12. The memory system of claim 11 , wherein the controller is configured to reconstruct memory values in the memory using the summed values via a simplex or interior-point method of linear programming.

13. The memory system of claim 11 , wherein the controller creates the sampling pattern taking into account factors for reconstructing the memory values and the upper bound for the number of locations.

14. The memory system of claim 9 further comprising:
reconstructing the memory constructed from the locations with non-zero summed values.

15. The memory system of claim 9 , wherein a constraint is based on at least one of an amount of power, a voltage, a current, or a physical limit on parallel reads for a memory device.

16. The memory system of claim 9 , wherein the memory is selected from one of a cross point memory, a cross bar memory, a dynamic random access memory, an optical memory, and a quantum memory.

17. A method for accessing a memory for a data processing system, the method comprising:
selecting, by a controller, a plurality of memory locations according to a sampling pattern, wherein the sampling patterns occurs within an upper bound indicating a maximum number of locations that may be read in parallel from the memory;
designating, by the controller, the plurality of locations in the memory as a base portion of locations;
sending, by the controller, a read request to the memory to read the plurality of locations in parallel according to the sampling pattern;
receiving from the memory, by the controller, a summed value of respective binary values in the plurality of locations in the memory according to a summation function in the memory;
if the summed value received from the memory is zero, cease using those locations to read the memory;
if the summed value received from the memory is non-zero and more than one location is present, dividing, by the controller, the base portion into a plurality of smaller portions of locations;
designating, by the controller, each smaller portion of locations as new respective base portions;
sending, by the controller, read requests for the locations in each new base portion; and
iteratively repeating, by the controller, the steps of dividing base portions with non-zero summed values and more than one location into smaller respective base portions and sending read requests for locations in the new base portions, until there are no unread base portions in the memory with non-zero sums and more than one location; and
reconstructing, by the controller

Assignees

• Nat Tech & Eng Solutions Sandia Llc

Inventors

• James Conrad D
• Quach Tu-Thach
• Agarwal Sapan
• Aimone James Bradley

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F3/0638

  Organizing or formatting or addressing of data · CPC title

• G06F2212/1052

  Security improvement · CPC title

• G06F9/52 Primary

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title