Dynamic adaptive clocking for non-common-clock interfaces

Patent metadata

Field	Value
Publication number	US-10649484-B2
Application number	US-201815960074-A
Country	US
Kind code	B2
Filing date	Apr 23, 2018
Priority date	Sep 25, 2015
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

The present disclosure provides devices and techniques to dynamically change the operating frequency of an interface where components on the interface have non-common clocks. An interface component may be provided with a frequency negotiation component to negotiate a shift in an operating frequency with other component on an interface where the different components have non-common clocks.

First claim

What is claimed is:

1. An apparatus comprising:
a host interface to exchange signals with a component interface over a bus, the host interface to operate based on a first reference clock and the component interface to operate based on a second reference clock different that the first reference clock; and
circuitry coupled to the host interface, the circuitry to:
send a first control signal to the component interface, the first control signal comprising an indication to change an operating frequency of the component interface,
receive, from the component interface, an indication that the component interface is ready to change the operating frequency of the component interface,
activate a transient frequency compensation for the bus, and
dynamically change an operating frequency of the host interface.

2. The apparatus of claim 1 , the circuitry to dynamically change the operating frequency of the host interface from a first operating frequency to a second operating frequency different than the first operating frequency, the first control signal to include an indication of the second operating frequency.

3. The apparatus of claim 1 , the circuitry to:
determine whether the operating frequency of the component interface has been changed; and
deactivate the transient frequency compensation and activate a steady-state frequency compensation based on a determination that the operating frequency of the component interface has been changed.

4. The apparatus of claim 1 , the circuitry to:
identify an amount of electromagnetic interference (EMI) or radio frequency interference (RFI) effects on the bus;
determine whether the amount of EMI or RFI effects on the bus exceed a threshold level; and
send, responsive to a determination that the amount of EMI or RFI effects on the bus exceed the threshold level, the first control signal to the component interface.

5. The apparatus of claim 1 , comprising the first reference clock.

6. The apparatus of claim 1 , the circuitry to:
send, from the host interface to a second component interface via the bus, a second control signal to include an indication to change an operating frequency of the second component interface, the second component interface to operate based on a third reference clock different than the first reference clock or the second reference clock;
receive, from the second component interface, an indication that the second component interface is ready to change the operating frequency of the second component interface;
activate the transient frequency compensation for the bus based receiving the indication from the component interface and the second component interface; and
dynamically change the operating frequency of the host interface based on receiving the indication from the component interface and the second component interface.

7. The apparatus of claim 6 , the circuitry to:
determine whether the operating frequency of the second component interface has been changed; and
deactivate the transient frequency compensation and activating a steady-state frequency compensation based on a determination that the operating frequency of the component interface and the operating frequency of the second component interface have been changed.

8. A computer-implemented method comprising:
sending, from a host interface to a component interface via a bus, a first control signal to include an indication to change an operating frequency of the component interface, the host interface to operate based on a first reference clock and the component interface to operate based on a second reference clock different than the first reference clock;
receiving, from the component interface, an indication that the component interface is ready to change the operating frequency of the component interface;
activating a transient frequency compensation for the bus; and
dynamically change an operating frequency of the host interface.

9. The computer-implemented method of claim 8 , the first control signal to include an indication to dynamically change the operating frequency of the component interface from a first frequency to a second frequency different than the first frequency.

10. The computer-implemented method of claim 8 , comprising:
determining whether the operating frequency of the component interface has been changed; and
deactivating the transient frequency compensation and activating a steady-state frequency compensation based on a determination that the operating frequency of the component interface has been changed.

11. The computer-implemented method of claim 8 , comprising:
identifying an amount of electromagnetic interference (EMI) or radio frequency interference (RFI) effects on the bus;
determining whether the amount of EMI or RFI effects on the bus exceed a threshold level; and
sending, responsive to a determination that the amount of EMI or RFI effects on the bus exceed the threshold level, the first control signal to the component interface.

12. The computer-implemented method of claim 8 , comprising:
sending, from the host interface to a second component interface via the bus, a second control signal to include an indication to change an operating frequency of the second component interface, the second component interface to operate based on a third reference clock different than the first reference clock or the second reference clock;
receiving, from the second component interface, an indication that the second component interface is ready to change the operating frequency of the second component interface;
activating the transient frequency compensation for the bus based receiving the indication from the component interface and the second component interface; and
dynamically changing the operating frequency of the host interface based on receiving the indication from the component interface and the second component interface.

13. The computer-implemented method of claim 12 , comprising:
determining whether the operating frequency of the second component interface has been changed; and
deactivating the transient frequency compensation and activating a steady-state frequency compensation based on a determination that the operating frequency of the component interface and the operating frequency of the second component interface have been changed.

14. At least one machine-readable storage medium comprising instructions that when executed by processing circuitry of a host interface, cause the processing circuitry to:
send, from the host interface to a component interface via a bus, a first control signal to include an indication to change an operating frequency of the component interface, the host interface to operate based on a first reference clock and the component interface to operate based on a second reference clock different than the first reference clock;
receive, from the component interface, an indication that the component interface is ready to change the operating frequency of the component interface;
activate a transient frequency compensation for the bus; and
dynamically change an operating frequency of the host interface.

15. The at least one machine-readable storage medium of claim 14 , the first control signal to include an indication to dynamically change the operating frequency of the component interface from a first frequency to a second frequency different than the first frequency.

16. The at least one machine-readable storage medium of claim 14 , the instructions, when executed, cause the processing circuitry to:
determine whether the operating frequency of the component interface has been

Assignees

• Intel Corp

Inventors

• Mukker Anoop
• Ooi Eng Hun
• Royer Jr Robert J
• Mcfarlane Brian R

Classifications

• H04J3/0697

  Synchronisation in a packet node · CPC title

• G06F13/40

  Bus structure {(for computer networks G06F15/163; for optical bus networks H04B10/25)} · CPC title

• G06F13/4291

  using a clocked protocol · CPC title

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title