Elementary electronic circuit for stage of amplification or repeat of analog signals

Patent metadata

Field	Value
Publication number	US-10644690-B2
Application number	US-201615757972-A
Country	US
Kind code	B2
Filing date	Sep 21, 2016
Priority date	Sep 28, 2015
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

An electronic circuit includes at least one first multi-gate transistor including a first gate and a second gate different from the first gate; and a regulation unit designed to measure a variable representing the drain-source voltage of the first transistor and to apply a polarization potential as a function of the variable to the second gate of the first transistor.

First claim

The invention claimed is:

1. An electronic circuit comprising:
at least one first multi-gate MOS transistor comprising a first gate and a second gate different from the first gate; and
a regulation unit comprising analog circuits and/or digital circuits, configured for applying to the second gate of the first transistor a bias potential which is a function of a quantity representative of a drain-source voltage of the first transistor,
wherein variations of the bias potential applied by the regulation unit according to variations of the drain-source voltage of the first transistor follow a law selected so that, in a range of drain-source voltages where the first transistor operates in saturation state, an output conductance of the first transistor is smaller than when a constant bias potential is applied to the second gate of the first transistor.

2. The circuit of claim 1 , wherein the variations of the bias potential applied by the regulation unit according to the variations of the drain-source voltage of the first transistor follow a law selected so that, in said range of drain-source voltages where the first transistor operates in saturation state, the output conductance of the first transistor is substantially independent from its drain-source voltage.

3. The circuit of claim 1 , wherein the variations of the bias potential applied by the regulation unit according to the variations of the drain-source voltage of the first transistor follow a law selected so that, for a given voltage applied between the first gate and a source of the first transistor, a drain-source current of the first transistor is substantially constant in said range of drain-source voltages where the first transistor operates in saturation state.

4. The circuit of claim 1 , wherein the first transistor comprises a channel-forming region, a source region, and a drain region laterally bordering the channel-forming region, the first gate being arranged above the channel-forming region and being insulated from the channel-forming region by an insulating layer, and the second gate being arranged under the channel-forming region.

5. The circuit of claim 4 , wherein the second gate is insulated from the channel-forming region by an insulating layer.

6. The circuit of claim 1 , wherein the first transistor is a FDSOI-type transistor.

7. The circuit of claim 1 , wherein the regulation unit comprises a second MOS transistor comprising:
a gate coupled to a drain of the first transistor;
a drain coupled to a node of application of a first power supply potential by a first resistor;
a source coupled to a node of application of a second power supply potential different from the first power supply potential by a second resistor.

8. The circuit of claim 1 , wherein the regulation unit comprises digital circuits.

9. The circuit of claim 1 , comprising a plurality of first multi-gate MOS transistors each comprising a first gate and a second gate different from the first gate, wherein the regulation unit is capable of measuring, for each first transistor, a quantity representative of the drain-source voltage of the transistor, and of applying to the second gate of each first transistor a bias potential which is a function of one or a plurality of said quantities.

10. The circuit of claim 1 , wherein the regulation unit comprises a calibration unit capable of determining the law of the variations to be applied to the bias potential according to the variations of the drain-source voltage of the first transistor so that, in saturation state, the output conductance of the first transistor is smaller than when a constant bias potential is applied to the second gate of the first transistor.

11. The circuit of claim 10 , wherein the regulation unit is reconfigurable, the calibration unit being capable of configuring the regulation unit to apply the determined law.

12. The circuit of claim 1 , wherein the regulation unit comprises a calibration unit capable of determining the law of the variations to be applied to the bias potential according to the variations of the drain-source voltage of the first transistor so that, in saturation state, the output conductance of the first transistor is substantially independent from its drain-source voltage.

13. The circuit of claim 1 , wherein the regulation unit comprises a third multi-gate MOS transistor comprising a first gate and a second gate different from the first gate, the first and third transistors being assembled as a current mirror, and the second gate of the first transistor being connected to a drain of the third transistor.

14. The circuit of claim 13 , wherein the second gate of the third transistor is connected to a drain of the first transistor.

15. An analog signal amplification circuit comprising at least one circuit of claim 1 .

16. A current copying circuit, comprising at least one circuit of claim 1 .

17. A differential signal amplification or copying circuit comprising at least one circuit of claim 1 .

Assignees

• Commissariat Energie Atomique
• Univ Nice Sophia Antipolis

Inventors

• Audebert Patrick
• De Foucauld Emeric
• Leduc Yves
• Jacquemod Gilles
• Wei Zhaopeng
• Lorenzini Philippe

Classifications

• H03K2217/0018

  Special modifications or use of the back gate voltage of a FET · CPC title

• G05F3/262

  using field-effect transistors only · CPC title

• G05F3/205

  Substrate bias-voltage generators (for static stores G11C5/146) · CPC title

• H03K17/0822 Primary

  in field-effect transistor switches · CPC title