Voltage buffer for input voltages above a supply voltage or below ground voltage

Patent metadata

Field	Value
Publication number	US-10644659-B2
Application number	US-201816111679-A
Country	US
Kind code	B2
Filing date	Aug 24, 2018
Priority date	Aug 24, 2018
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

A buffer amplifier comprises a source follower and a feedback amplifier. The feedback amplifier may be configured to control a drain current of the source follower to remain substantially constant independent of a load.

First claim

The invention claimed is:

1. Apparatus, comprising:
a buffer amplifier comprising a source follower and a feedback amplifier, the feedback amplifier configured to control a drain current of the source follower to remain substantially constant independent of a load, wherein the buffer amplifier is coupled to an input voltage based upon a line voltage and to a supply voltage derived from the input voltage.

2. The apparatus of claim 1 , wherein the buffer amplifier presents an output impedance based upon the feedback amplifier.

3. The apparatus of claim 1 , wherein the buffer amplifier further comprises a plurality of MOSFETs, wherein at least one of the plurality of MOSFETs is coupled to the source follower and wherein the feedback amplifier is configured to control the drain current of the source follower to match a drain current of the at least one of the plurality of MOSFETs.

4. The apparatus of claim 1 , wherein the feedback amplifier is further configured to control a voltage of a drain of the source follower.

5. The apparatus of claim 4 , wherein the controlled voltage of the drain of the source follower is within approximately 300 mV of the supply voltage.

6. The apparatus of claim 1 , wherein a common mode voltage associated with the input voltage is greater than the supply voltage.

7. The apparatus of claim 1 , wherein a common mode voltage associated with the input voltage is within approximately 300 mV of the supply voltage.

8. The apparatus of claim 1 , further comprising an attenuator coupled to an input of the buffer amplifier, wherein the attenuator comprises at least one resistor.

9. The apparatus of claim 8 , wherein an input impedance presented by the buffer amplifier is effectively 1000 times greater than an output impedance presented by the attenuator.

10. The apparatus of claim 1 , wherein an output of the source follower of the buffer amplifier is coupled to a variable gain amplifier.

11. The apparatus of claim 10 , wherein an impedance presented by an input of the variable gain amplifier is effectively 1000 times greater than an output impedance presented by the buffer amplifier.

12. The apparatus of claim 1 , wherein the buffer amplifier is realized in an integrated circuit.

13. The apparatus of claim 1 , wherein the feedback amplifier comprises a MOSFET coupled to a source of the source follower of the buffer amplifier.

14. The apparatus of claim 13 , further comprising a capacitor coupled between a drain of the source follower and a gate of the MOSFET, wherein the capacitor is configured to control a frequency response of the buffer amplifier.

15. The apparatus of claim 1 , wherein the feedback amplifier comprises at least two source followers.

16. The apparatus of claim 15 , wherein a gate of a first source follower of the feedback amplifier is coupled to a reference voltage, and a gate of a second source follower of the feedback amplifier is coupled to a drain voltage of the source follower of the buffer amplifier.

17. The apparatus of claim 16 , wherein the drain voltage is within approximately 100 mV of the reference voltage.

18. The apparatus of claim 16 , wherein the first and second source followers of the feedback amplifier are coupled to a differential amplifier.

19. The apparatus of claim 18 , wherein the first and second source followers of the feedback amplifier are configured to shift at least one voltage of a differential pair at an input of the differential amplifier so that a voltage of the differential pair is in an operating region of the differential amplifier.

20. A power monitoring circuit to monitor a line voltage associated with a power source, comprising:
a buffer amplifier comprising a source follower and a feedback amplifier, the feedback amplifier configured to control a drain current of the source follower to remain substantially constant independent of a load; and
a chopper circuit coupled to an input of the buffer amplifier.

21. The power monitoring circuit of claim 20 , wherein the buffer amplifier is coupled to an input voltage derived from the line voltage and to a supply voltage derived from the line voltage.

22. The power monitoring circuit of claim 21 , wherein a common mode voltage associated with the input voltage is greater than the supply voltage.

23. The power monitoring circuit of claim 21 , wherein a common mode voltage associated with the input voltage is within approximately 300 mV of the supply voltage.

24. The power monitoring circuit of claim 21 , wherein the supply voltage is an AC voltage.

25. The power monitoring circuit of claim 21 , wherein the supply voltage is a DC voltage.

26. The power monitoring circuit of claim 20 , wherein an input impedance presented by the buffer amplifier is effectively greater than 100 MOhms.

27. The power monitoring circuit of claim 20 , wherein an output impedance presented by the buffer amplifier is effectively less than 100Ω.

28. The power monitoring circuit of claim 20 , further comprising a variable gain amplifier coupled to an output of the buffer amplifier.

29. The power monitoring circuit of claim 28 , wherein an output of the variable gain amplifier is coupled to an analog-to-digital converter.

30. The power monitoring circuit of claim 29 , wherein the analog-to-digital converter comprises a sigma-delta modulator.

31. The power monitoring circuit of claim 29 , wherein an output of the analog-to-digital converter is coupled to a digital signal processor.

32. The power monitoring circuit of claim 20 , wherein the power monitoring circuit is realized in an integrated circuit.

33. Apparatus comprising:
means for controlling a drain current of a source follower in a buffer amplifier to remain substantially constant independent of a load, wherein the buffer amplifier is coupled to an input voltage based upon a line voltage and to a supply voltage derived from the input voltage; and
means for controlling an output impedance of the buffer amplifier.

34. The apparatus of claim 33 , further comprising:
means for controlling the drain current of the source follower to match a drain current of at least one of a plurality of MOSFETs in the buffer amplifier.

35. The apparatus of claim 33 , further comprising:
means for controlling a voltage at a drain of the source follower.

36. The apparatus of claim 33 , further comprising:
means for shifting an output voltage of the buffer amplifier.

37. The apparatus of claim 33 , further comprising:
means for controlling a capacitance of the source follower.

Assignees

• Allegro Microsystems Llc

Inventors

• Choe Soo-Chang
• Petrie Craig S

Classifications

• H03F3/393

  with field-effect devices · CPC title

• H03F2200/69

  the amplifier stage being a common drain coupled MOSFET, i.e. source follower · CPC title

• H03F2203/45562

  the IC comprising a cross coupling circuit, e.g. comprising two cross-coupled transistors · CPC title

• H03F2203/45591

  the IC comprising one or more potentiometers · CPC title

• H03F3/50

  Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower · CPC title