Power converter controller

Patent metadata

Field	Value
Publication number	US-10644595-B2
Application number	US-201916378837-A
Country	US
Kind code	B2
Filing date	Apr 9, 2019
Priority date	Dec 8, 2017
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

A circuit, comprising a trapezoidal generator that comprises digital logic configured to couple at a first input to a loop controller and at a second input to a buck-boost region detector and a driver coupled to an output of the digital logic and configured to couple to at least one power transistor of a power converter.

First claim

What is claimed is:

1. A power converter controller comprising:
a loop controller configured to monitor an inductor current of an inductor associated with a power converter and generate a control signal based on the inductor current;
a detector configured to determine whether the power converter is operating in a buck-boost region; and
a gate driver coupled to the loop controller and the detector, the gate driver configured to control the power converter according to a trapezoidal control pattern based on the control signal when the detector indicates that the power converter is operating in the buck-boost region.

2. The power converter controller of claim 1 , wherein the loop controller is configured to monitor the inductor current and a feedback signal representative of an output voltage of the power converter and generate the control signal based on the inductor current and the feedback signal.

3. The power converter controller of claim 1 , wherein the gate driver comprises:
a driver configured to generate a gate driver signal for driving the power converter; and
digital logic coupled to the detector and the driver, the digital logic configured to control the driver to generate a gate drive signal according to the trapezoidal control pattern when the detector indicates that the power converter is operating in the buck-boost region.

4. The power converter controller of claim 1 , wherein the trapezoidal control pattern includes an on-time (Ton) during which the inductor is charged, an off-time (Toff) during which the inductor is discharged, and at least one common mode time during which an input associated with the power converter is coupled to an output of the power converter through the inductor.

5. The power converter controller of claim 1 , wherein the detector is configured to determine whether the power converter is operating in the buck-boost region according to an input voltage of the power converter and an output voltage of the power converter.

6. The power converter controller of claim 1 , wherein the detector is configured to determine whether the power converter is operating in the buck-boost region according to an input voltage of the power converter and the inductor current of the inductor associated with the power converter.

7. The power converter controller of claim 1 , wherein the detector is configured to determine whether the power converter is operating in the buck-boost region according to an output voltage of the power converter and the inductor current of the inductor associated with the power converter.

8. A power converter controller comprising:
a loop controller configured to monitor a feedback signal representative of an output voltage of a power converter and generate a control signal based on the feedback signal;
a detector configured to determine whether the power converter is operating in a buck-boost region; and
a gate driver coupled to the loop controller and the detector, the gate driver configured to control the power converter according to a trapezoidal control pattern based on the control signal when the detector indicates that the power converter is operating in the buck-boost region.

9. The power converter controller of claim 8 , wherein the loop controller is configured to monitor the feedback signal and an inductor current of an inductor associated with the power converter and generate the control signal based on the feedback signal and the inductor current.

10. The power converter controller of claim 8 , wherein the gate driver comprises:
a driver configured to generate a gate driver signal for driving the power converter; and
digital logic coupled to the detector and the driver, the digital logic configured to control the driver to generate a gate drive signal according to the trapezoidal control pattern when the detector indicates that the power converter is operating in the buck-boost region.

11. The power converter controller of claim 8 , wherein the trapezoidal control pattern includes an on-time (Ton) during which an inductor associated with the power converter is charged, an off-time (Toff) during which the inductor is discharged, and at least one common mode time during which an input associated with the power converter is coupled to an output of the power converter through the inductor.

12. The power converter controller of claim 8 , wherein the detector is configured to determine whether the power converter is operating in the buck-boost region according to an input voltage of the power converter and the output voltage of the power converter.

13. The power converter controller of claim 8 , wherein the detector is configured to determine whether the power converter is operating in the buck-boost region according to an input voltage of the power converter and an inductor current of an inductor associated with the power converter.

14. The power converter controller of claim 8 , wherein the detector is configured to determine whether the power converter is operating in the buck-boost region according to the output voltage of the power converter and an inductor current of an inductor associated with the power converter.

15. A power converter controller comprising:
a detector configured to generate a buck-boost signal upon determining a power converter is operating in a buck-boost region; and
a gate driver coupled to the detector, and configured:
generate a first driver signal for charging an inductor of the power converter during a power transistor on-time (Ton) when the buck-boost signal is not asserted;
generate a second driver signal for discharging the inductor of the power converter during a power transistor off-time (Toff) when the buck-boost signal is not asserted; and
generate a third driver signal for coupling an input of the power converter to an output of the power converter via the inductor during a common mode time when the buck-boost signal is asserted.

16. The power converter controller of claim 15 , wherein the common mode time is between Ton and Toff.

17. The power converter controller of claim 15 , wherein the gate driver is configured to cyclically deliver the first, second, third driver signals to the power converter for generating a trapezoidal inductor current pattern.

18. The power converter controller of claim 15 , further comprising:
a loop controller configured to monitor an inductor current of the and generate a control signal based on the inductor current,
wherein the gate driver is configured to generate the second driver signal based on the control signal and the buck-boost signal.

19. The power converter controller of claim 15 , further comprising:
a loop controller configured to monitor a feedback signal representative of an output voltage of the power converter of the and generate a control signal based on the inductor current,
wherein the gate driver is configured to generate the second driver signal based on the feedback signal and the buck-boost signal.

20. The power converter controller of claim 15 , wherein:
the third driver signal is configured to turn on a first power transistor of the power converter to enable a first conductive path between the input and a first terminal of the inductor; and
the third driver signal is configured to turn on a second power transistor of the power converter to enable a second conductive path between a second terminal of the inductor and the output.

Assignees

• Texas Instruments Inc

Inventors

• Sharma Anmol
• Prexl Franz

Classifications

• H02M3/157 Primary

  with digital control · CPC title

• H02M1/088

  for the simultaneous control of series or parallel connected semiconductor devices · CPC title

• G05F1/575

  characterised by the feedback circuit · CPC title

• H03K4/063

  high voltage - or current generators · CPC title

• H02M3/1582

  Buck-boost converters (H02M3/1584 takes precedence) · CPC title