Quantum dot array devices

Patent metadata

Field	Value
Publication number	US-10644113-B2
Application number	US-201616316971-A
Country	US
Kind code	B2
Filing date	Aug 10, 2016
Priority date	Aug 10, 2016
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; and a plurality of gates disposed above the quantum well stack, wherein individual ones of the plurality of gates have a footprint shape with two opposing linear faces and two opposing curved faces.

First claim

The invention claimed is:

1. A quantum dot device, comprising:
a quantum well stack including a quantum well layer; and
a plurality of gates disposed above the quantum well stack, wherein individual ones of the plurality of gates have a footprint shape with two opposing linear faces and two opposing curved faces.

2. The quantum dot device of claim 1 , wherein at least two of the gates are spaced apart in a first dimension above the quantum well stack, at least two of the gates are spaced apart in a second dimension above the quantum well stack, and the first and second dimensions are perpendicular.

3. The quantum dot device of claim 2 , further comprising:
an insulating material disposed above the quantum well stack, wherein the insulating material extends between at least two of the gates spaced apart in the first dimension, and the insulating material extends between at least two of the gates spaced apart in the second dimension.

4. The quantum dot device of claim 3 , wherein the insulating material includes a plurality of individual openings in which individual ones of the gates are disposed.

5. The quantum dot device of claim 1 , wherein the plurality of gates are arranged in an n×m array, n is greater than 1, and m is greater than 1.

6. The quantum dot device of claim 1 , wherein the plurality of gates is a plurality of first gates, the quantum well layer is a first quantum well layer, the quantum well stack includes a second quantum well layer, and the quantum dot device further includes:
a plurality of second gates disposed below the quantum well stack, wherein the second quantum well layer is disposed between the plurality of second gates and the first quantum well layer.

7. The quantum dot device of claim 6 , wherein at least two of the second gates are spaced apart in the first dimension below the quantum well stack, and at least two of the second gates are spaced apart in the second dimension below the quantum well stack.

8. The quantum dot device of claim 7 , wherein individual ones of the first gates above the quantum well stack correspond to individual ones of the second gates below the quantum well stack.

9. The quantum dot device of claim 1 , wherein the quantum well layer is formed of silicon or germanium.

10. The quantum dot device of claim 1 , wherein the plurality of gates includes:
a first gate having a first length,
two second gates arranged such that the first gate is disposed between the second gates, wherein the second gates have a second length different from the first length, and
two third gates arranged such that the second gates are disposed between the third gates, wherein the third gates have a third length different from the first length and different from the second length.

11. The quantum dot device of claim 1 , wherein individual gates of the plurality of gates include a gate dielectric having a U-shaped cross section.

12. A method of manufacturing a quantum dot device, comprising:
providing a quantum well stack;
forming a patterned template material above the quantum well stack, wherein the patterned template material includes a plurality of openings having a footprint shape with two opposing linear faces and two opposing curved faces; and
forming a plurality of gates above the quantum well stack, wherein individual ones of the gates are at least partially disposed in corresponding individual ones of the openings.

13. The method of claim 12 , wherein forming the template material includes:
providing unpatterned template material above the quantum well stack;
providing a first mask above the unpatterned template material;
forming a plurality of parallel trenches oriented in the first mask to form a patterned first mask;
filling the plurality of parallel trenches with a fill material;
forming a plurality of openings in the fill material; and
patterning the unpatterned template material in accordance with the plurality of openings.

14. The method of claim 13 , wherein forming the plurality of openings including exposing the fill material using extreme ultraviolet lithography.

15. The method of claim 13 , further comprising:
providing a second mask above the unpatterned template material; and
patterning the second mask in accordance with the plurality of openings;
wherein patterning the unpatterned template material includes patterning the unpatterned template material in accordance with the patterned second mask.

16. The method of claim 12 , wherein forming the patterned template material includes using a spacer-based pitch-quartering technique or a spacer-based pitch-halving technique.

17. The method of claim 12 , wherein the plurality of gates are formed above a first face of the quantum well stack, and the method further comprises:
forming another set of gates above a second face of the quantum well stack, wherein the second face of the quantum well stack is opposite to the first face of the quantum well stack.

18. A quantum computing device, comprising:
a quantum processing device, wherein the quantum processing device includes an active quantum well layer and a read quantum well layer, a first set of gates to control formation of quantum dots in the active quantum well layer, and a second set of gates to control formation of quantum dots in the read quantum well layer, and wherein the first set of gates includes individual gates having a footprint shape with two opposing linear faces and two opposing curved faces;
a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the first set of gates and the second set of gates; and
a memory device to store data generated by the read quantum well layer during operation of the quantum processing device.

19. The quantum computing device of claim 18 , wherein the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.

20. The quantum computing device of claim 18 , wherein the first set of gates and the second set of gates each include a plurality of gates arranged in a two-dimensional array.

Assignees

• Intel Corp

Inventors

• Clarke James S
• Bristol Robert L
• Pillarisetty Ravi
• Roberts Jeanette M
• George Hubert C
• Thomas Nicole K

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/66977

  Electricity · mapped topic

• H01L29/80

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L29/7613

  Electricity · mapped topic