Array substrate, fabrication method thereof, driving transistor and display panel

Patent metadata

Field	Value
Publication number	US-10644035-B2
Application number	US-201715769492-A
Country	US
Kind code	B2
Filing date	Nov 3, 2017
Priority date	Mar 10, 2017
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

An array substrate includes a pixel circuit and a light-emitting diode. The pixel circuit includes a driving transistor including a first active medium made of polysilicon, and a switching transistor including a second active medium made of polysilicon. The first active medium has a first grain size. The second active medium has a second grain size larger than the first grain size. The light-emitting diode is coupled to the pixel circuit.

First claim

What is claimed is:

1. A method for fabricating an array substrate, comprising:
fabricating a pixel circuit, the pixel circuit including:
a driving transistor including a first active medium made of polysilicon, the first active medium having a first grain size; and
a switching transistor including a second active medium made of polysilicon, the second active medium having a second grain size larger than the first grain size; and
fabricating an organic light-emitting diode coupled to the pixel circuit;
wherein fabricating the pixel circuit includes:
forming an amorphous silicon layer over a substrate;
forming a gate insulating layer over the amorphous silicon layer;
forming a preset pattern over the gate insulating layer, an orthogonal projection of the preset pattern on the substrate overlapping an orthogonal projection of the first active medium on the substrate and not overlapping with an orthogonal projection of the second active medium on the substrate;
performing laser annealing to turn the amorphous silicon layer into a polysilicon layer;
removing the preset pattern; and
forming the driving transistor and the switching transistor based on the polysilicon layer and the gate insulating layer;
wherein removing the preset pattern includes applying a preset etching solution capable of etching the preset pattern and the gate insulating layer to remove the preset pattern and reduce a thickness of a region of the gate insulating layer not covered by the preset pattern.

2. The method according to claim 1 , wherein forming the driving transistor and the switching transistor includes:
patterning the polysilicon layer and the gate insulating layer to form:
a polysilicon pattern including the first active medium and the second active medium, and
a gate insulating pattern including a first gate insulating block stacked over the first active medium and a second gate insulating block stacked over the second active medium;
forming a gate electrode pattern over the gate insulating pattern, the gate electrode pattern including a first gate electrode stacked over the first gate insulating block and a second gate electrode stacked over the second gate insulating block;
forming an interlayer insulating layer over the gate electrode pattern; and
forming a source/drain electrode pattern over the interlayer insulating layer, the source/drain electrode pattern including:
a first source electrode and a first drain electrode coupled to the first active medium, and
a second source electrode and a second drain electrode coupled to the second active medium,
wherein:
the driving transistor includes the first gate electrode, the first source electrode, the first drain electrode, and the first active medium, and
the switching transistor includes the second gate electrode, the second source electrode, the second drain electrode, and the second active medium.

3. The method according to claim 2 , further comprising, before forming the interlayer insulating layer:
doping portions of the polysilicon pattern.

4. The method according to claim 3 , wherein forming the source/drain electrode pattern includes:
forming the first source electrode and the first drain electrode to be coupled to doped regions in the first active medium, and
forming the second source electrode and the second drain electrode to be coupled to doped regions in the second active medium.

5. The method according to claim 2 , wherein forming the preset pattern includes forming an amorphous silicon pattern.

6. A method for fabricating an array substrate, comprising:
fabricating a pixel circuit, the pixel circuit including:
a driving transistor including a first active medium made of polysilicon, the first active medium having a first grain size; and
a switching transistor including a second active medium made of polysilicon, the second active medium having a second grain size larger than the first grain size; and
fabricating an organic light-emitting diode coupled to the pixel circuit;
wherein fabricating the pixel circuit includes:
forming an amorphous silicon layer over a substrate;
forming a gate insulating layer over the amorphous silicon layer;
forming a preset pattern over the gate insulating layer, an orthogonal projection of the preset pattern on the substrate overlapping an orthogonal projection of the first active medium on the substrate and not overlapping with an orthogonal projection of the second active medium on the substrate;
performing laser annealing to turn the amorphous silicon layer into a polysilicon layer;
removing the preset pattern; and
forming the driving transistor and the switching transistor based on the polysilicon layer and the gate insulating layer;
wherein forming the preset pattern includes forming an amorphous silicon pattern.

7. The method according to claim 6 , wherein:
forming the amorphous silicon layer includes forming an amorphous silicon layer having a thickness of approximately 500 angstroms, and
forming the amorphous silicon pattern includes forming an amorphous silicon pattern having a thickness in a range from approximately 100 angstroms to approximately 200 angstroms.

8. A method for fabricating an array substrate, comprising:
fabricating a pixel circuit, the pixel circuit including:
a driving transistor including a first active medium made of polysilicon, the first active medium having a first grain size; and
a switching transistor including a second active medium made of polysilicon, the second active medium having a second grain size larger than the first grain size; and
fabricating an organic light-emitting diode coupled to the pixel circuit;
wherein fabricating the pixel circuit includes:
forming an amorphous silicon layer over a substrate;
forming a gate insulating layer over the amorphous silicon layer;
forming a preset pattern over the gate insulating layer, an orthogonal projection of the preset pattern on the substrate overlapping an orthogonal projection of the first active medium on the substrate and not overlapping with an orthogonal projection of the second active medium on the substrate;
performing laser annealing to turn the amorphous silicon layer into a polysilicon layer;
removing the preset pattern; and
forming the driving transistor and the switching transistor based on the polysilicon layer and the gate insulating layer;
wherein forming the driving transistor and the switching transistor includes:
patterning the polysilicon layer and the gate insulating layer to form:
a polysilicon pattern including the first active medium and the second active medium, and
a gate insulating pattern including a first gate insulating block stacked over the first active medium and a second gate insulating block stacked over the second active medium;
forming a gate electrode pattern over the gate insulating pattern, the gate electrode pattern including a first gate electrode stacked over the first gate insulating block and a second gate electrode stacked over the second gate insulating block;
forming an interlayer insulating layer over the gate electrode pattern; and
forming a source/drain electrode pattern over the interlayer insulating layer, the source/drain electrode pattern including:
a first source electrode and a first drain electrode coupled to the first active medium, and
a second source electrode and a second drain electrode coupled to the second active medium,
wherein:
the driving transistor includes the first gate electrode, the first source electrode, the first drain electrode, and the first active medium, and
the switching transistor includes the second gate electrode, the second source electrode, the second drain electrode, and the second active medium;
wherein the met

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Xu Wenqing
• Liu Mingxuan
• Wang Jing
• Zhang Xiaoxiang
• Guo Huibin

Classifications

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G3/3225

  using an active matrix · CPC title

• G09G2300/0439

  Pixel structures · CPC title

• H01L29/66757

  Electricity · mapped topic

• H01L29/78675

  Electricity · mapped topic