Mode converter and method of fabricating thereof

Patent metadata

Field	Value
Publication number	US-10643903-B2
Application number	US-201716317151-A
Country	US
Kind code	B2
Filing date	Jul 13, 2017
Priority date	Jul 13, 2016
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

An optical mode converter and method of fabricating the same from wafer including a double silicon-on-insulator layer structure. The method comprising: providing a first mask over a portion of a device layer of the DSOI layer structure; etching an unmasked portion of the device layer down to at least an upper buried oxide layer, to provide a cavity; etching a first isolation trench and a second isolation trench into a mode converter layer, the mode converter layer being: on an opposite side of the upper buried oxide layer to the device layer and between the upper buried oxide layer and a lower buried oxide layer, the lower buried oxide layer being above a substrate; wherein the first isolation trench and the second isolation trench define a tapered waveguide; filling the first isolation trench and the second isolation trench with an insulating material, so as to optically isolate the tapered waveguide from the remaining mode converter layer; and regrowing the etched region of the device layer.

First claim

The invention claimed is:

1. A method of fabricating an optical mode converter from a wafer including a double silicon-on-insulator (DSOI) layer structure, comprising the steps of:
providing a first mask over a portion of a device layer of the DSOI layer structure;
etching an unmasked portion of the device layer down to at least an upper buried oxide layer, to provide a cavity;
etching, after the etching of the unmasked portion of the device layer, a first isolation trench and a second isolation trench into a mode converter layer, the mode converter layer being:
on an opposite side of the upper buried oxide layer from the device layer and between the upper buried oxide layer and a lower buried oxide layer, the lower buried oxide layer being above a substrate;

wherein the first isolation trench and the second isolation trench define a tapered waveguide;
filling the first isolation trench and the second isolation trench with an insulating material, so as to optically isolate the tapered waveguide from the remaining mode converter layer; and
regrowing the etched region of the device layer.

2. The method of claim 1 , further comprising a step of:
etching a rib waveguide from the regrown region of the device layer.

3. The method of claim 1 , wherein the step of etching the unmasked portion of the device layer down to at least the upper buried oxide layer comprises:
a first etching step, etching from an upper surface of the device layer to an upper surface of the upper buried oxide layer; and
a second etching step, etching from an upper surface of the upper buried oxide layer to an upper surface of the mode converter layer.

4. The method of claim 3 , wherein the second etching step does not remove all of the buried oxide layer in the cavity.

5. The method of claim 1 , further comprising a step, between the steps of etching the unmasked portion and etching the first and second isolation trenches, of:
depositing an oxidation barrier over: (i) the first mask and (ii) the cavity, wherein the cavity is defined by sidewalls and a bed.

6. The method of claim 5 , wherein the step of filling the first isolation trench and the second isolation trench comprises:
thermally oxidizing the mode converter layer, so as to fill the first isolation trench and the second isolation trench with an oxide.

7. The method of claim 1 , further comprising a step, after regrowing the etched region of the device layer, of:
planarizing the regrown region of the device layer such that it is coplanar with an uppermost surface of the unetched region of the device layer.

8. The method of claim 1 , wherein the tapered waveguide is provided with a first width of between 9 μm and 15 μm and a second width of less than 1 μm.

9. The method of claim 1 , wherein a width of the cavity etched is substantially wider than a widest width of the tapered waveguide.

10. The method of claim 1 , further comprising a step of:
etching a v-groove interface at a first end of the mode converter, such that an input facet of the tapered waveguide overhangs the v-groove interface, so as to allow passive alignment of a fiber optical cable to the tapered waveguide.

11. The method of claim 1 , further comprising a step of:
polishing a first end of the tapered waveguide, so as to provide a planar input facet for active alignment to a fiber optic cable.

12. A method of fabricating an optical mode converter from a wafer including a double silicon-on-insulator (DSOI) layer structure, comprising the steps of:
providing a first mask over a portion of a device layer of the DSOI layer structure;
etching an unmasked portion of the device layer from an upper surface of the device layer to an upper surface of an upper buried oxide layer, to provide a cavity;
etching from an upper surface of the upper buried oxide layer in the cavity to an upper surface of the mode converter layer, wherein the etching does not remove all of the upper buried oxide layer in the cavity;
etching a first isolation trench and a second isolation trench into a mode converter layer, the mode converter layer being on an opposite side of the upper buried oxide layer from the device layer and between the upper buried oxide layer and a lower buried oxide layer, the lower buried oxide layer being above a substrate;
wherein the first isolation trench and the second isolation trench define a tapered waveguide;
filling the first isolation trench and the second isolation trench with an insulating material, so as to optically isolate the tapered waveguide from the remaining mode converter layer; and
regrowing the etched region of the device layer.

13. The method of claim 12 , further comprising a step of:
etching a rib waveguide from the regrown region of the device layer.

14. The method of claim 12 , further comprising a step, between the steps of etching an unmasked portion of the device layer and etching the first and second isolation trenches, of:
depositing an oxidation barrier over: (i) the first mask and (ii) the cavity, wherein the cavity is defined by sidewalls and a bed.

15. The method of claim 14 , wherein the step of filling the first isolation trench and the second isolation trench comprises:
thermally oxidizing the mode converter layer, so as to fill the first isolation trench and the second isolation trench with an oxide.

16. The method of claim 12 , further comprising a step, after regrowing the etched region of the device layer, of:
planarizing the regrown region of the device layer such that it is coplanar with an uppermost surface of the unetched region of the device layer.

17. The method of claim 12 , wherein the tapered waveguide is provided with a first width of between 9 μm and 15 μm and a second width of less than 1 μm.

18. The method of claim 12 , wherein a width of the cavity etched in the device layer is substantially wider than a widest width of the tapered waveguide.

19. The method of claim 12 , further comprising a step of:
etching a v-groove interface at a first end of the mode converter, such that an input facet of the tapered waveguide overhangs the v-groove interface, so as to allow passive alignment of a fiber optical cable to the tapered waveguide.

20. The method of claim 12 , further comprising a step of:
polishing a first end of the tapered waveguide, so as to provide a planar input facet for active alignment to a fiber optic cable.

Assignees

• Rockley Photonics Ltd

Inventors

• Drake John
• Lerose Damiana
• Nykänen Henri

Classifications

• G02B2006/12038

  Glass (SiO2 based materials) · CPC title

• G02B2006/12147

  Coupler · CPC title

• H01S5/0216

  using an intermediate compound, e.g. a glue or solder · CPC title

• G02B6/42

  Coupling light guides with opto-electronic elements · CPC title

• G02B6/305

  and having an integrated mode-size expanding section, e.g. tapered waveguide · CPC title