Systems and methods for rendering multiple levels of detail

Patent metadata

Field	Value
Publication number	US-10643296-B2
Application number	US-201614993685-A
Country	US
Kind code	B2
Filing date	Jan 12, 2016
Priority date	Jan 12, 2016
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

An electronic device is described. The electronic device includes a memory. The electronic device also includes a very long instruction word (VLIW) circuit. The VLIW circuit includes an asynchronous memory controller. The asynchronous memory controller is configured to asynchronously access the memory to render different levels of detail. The electronic device may include a non-uniform frame buffer controller configured to dynamically access different subsets of a frame buffer. The different subsets may correspond to the different levels of detail.

First claim

What is claimed is:

1. An electronic device, comprising:
a memory configured to store geometry data; and
a very long instruction word (VLIW) circuit comprising an asynchronous memory controller, wherein the asynchronous memory controller is configured to asynchronously access the memory to render different first and second geometric tessellated levels of detail for the geometry data in a single draw call, and wherein the electronic device comprises a non-uniform frame buffer including different subsets respectively corresponding to the different first and second geometric tessellated levels of detail, and wherein the VLIW circuit is configured to execute a first shader sub-routine that accesses a first frame buffer subset concurrently with a second shader sub-routine that accesses a second frame buffer subset and to swap the second shader sub-routine with a third shader sub-routine that accesses the second frame buffer subset while the first shader sub-routine is ongoing.

2. The electronic device of claim 1 , wherein the electronic device further comprises a non-uniform frame buffer controller configured to dynamically access the different subsets of the non-uniform frame buffer.

3. The electronic device of claim 2 , wherein the non-uniform frame buffer controller is configured to access at least one pixel of a first zone at a different rate from at least one pixel of a second zone, wherein the first zone and the second zone correspond to the different first and second geometric tessellated levels of detail.

4. The electronic device of claim 2 , wherein the non-uniform frame buffer controller is configured to enable shader sub-routine swapping when processing of a first pixel is ongoing and processing of a second pixel is completed.

5. The electronic device of claim 2 , where the non-uniform frame buffer controller is configured to substitute a processed first sample of a first pixel for a second sample of a second pixel to avoid processing the second sample of the second pixel, wherein the first pixel has a different number of samples than the second pixel.

6. The electronic device of claim 2 , wherein the non-uniform frame buffer controller is included in a composition/decomposition (C/D) block, included in the memory, or is separate from the C/D block and the memory.

7. The electronic device of claim 1 , wherein the VLIW circuit comprises a tessellation control shader (TCS), a tessellator (TESS), a tessellation evaluation shader (TES), a geometry shader (GS), a rasterizer, and a fragment shader (FS), and wherein one or more of the TCS, the TESS, the TES, the GS, the rasterizer, and the FS comprise the asynchronous memory controller.

8. The electronic device of claim 1 , wherein the memory is included in the VLIW circuit, and wherein the asynchronous memory controller is configured to access a level of detail (LOD) parameter in the memory asynchronously.

9. The electronic device of claim 1 , wherein the VLIW circuit comprises a tessellation control shader (TCS), a tessellator (TESS), a tessellation evaluation shader (TES), a geometry shader (GS), a rasterizer, a fragment shader (FS), and a tiler, and wherein one or more of the TCS, the TESS, the TES, the GS, the rasterizer, the FS, and the tiler comprise the asynchronous memory controller.

10. The electronic device of claim 1 , wherein the memory is system memory, and wherein the asynchronous memory controller is configured to access a level of detail (LOD) parameter in the memory asynchronously.

11. The electronic device of claim 1 , wherein the asynchronous memory controller is configured to asynchronously access parameter data during processing of a set of data.

12. The electronic device of claim 1 , wherein the VLIW circuit is configured to perform non-uniform level of detail tessellation across a zone boundary between a first zone and a second zone in a single data set, wherein the first zone and the second zone correspond to the different first and second geometric tessellated levels of detail.

13. The electronic device of claim 1 , wherein the VLIW circuit is configured to perform non-uniform level of detail tessellation in a single data set when a level of detail of the single draw call changes during processing the single data set based on eye tracking.

14. The electronic device of claim 1 , further comprising a display configured to present the different first and second geometric tessellated levels of detail.

15. The electronic device of claim 1 , wherein the non-uniform frame buffer is configured to store pixels with the different first and second geometric tessellated levels of detail in the different subsets of the non-uniform frame buffer.

16. The electronic device of claim 1 , further comprising a graphics pipeline comprising the VLIW circuit and a rasterizer, wherein the rasterizer is configured to generate pixel data based on the different tessellated levels of detail.

17. A method performed by an electronic device, the method comprising:
obtaining geometry data;
asynchronously accessing memory to render different first and second geometric tessellated levels of detail for the geometry data in a single draw call, wherein different subsets of a non-uniform frame buffer respectively correspond to the different first and second geometric tessellated levels of detail;
executing a first shader sub-routine that accesses a first frame buffer subset concurrently with a second shader sub-routine that accesses a second frame buffer subset; and
swapping the second shader sub-routine with a third shader sub-routine that accesses the second frame buffer subset while the first shader sub-routine is ongoing.

18. The method of claim 17 , further comprising dynamically accessing different subsets of the non-uniform frame buffer.

19. The method of claim 18 , further comprising accessing at least one pixel of a first zone at a different rate from at least one pixel of a second zone, wherein the first zone and the second zone correspond to the different first and second geometric tessellated levels of detail.

20. The method of claim 18 , further comprising swapping shader sub-routines when processing of a first pixel is ongoing and processing of a second pixel is completed.

21. The method of claim 17 , further comprising accessing a level of detail (LOD) parameter in the memory asynchronously.

22. The method of claim 17 , further comprising asynchronously accessing parameter data during processing of a set of data.

23. The method of claim 17 , further comprising performing non-uniform level of detail tessellation across a zone boundary between a first zone and a second zone in a single data set, wherein the first zone and the second zone correspond to the different first and second geometric tessellated levels of detail.

24. The method of claim 17 , further comprising performing non-uniform level of detail tessellation in a single data set when a level of detail of the single draw call changes during processing the single data set based on eye tracking.

25. The method of claim 17 , further comprising storing pixels with the different first and second geometric tessellated levels of detail in the different subsets of the non-uniform frame buffer.

26. A computer-program product, comprising a non-transitory tangible computer-readable medium having instructions thereon, the instructions comprising:
code for causing an electronic device to obtain geometry data;

Assignees

• Qualcomm Inc

Inventors

• Nguyen Phi Hung
• Bi Ning

Classifications

• G09G5/006

  Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04) · CPC title

• G06T15/10

  Geometric effects · CPC title

• G09G2340/0407

  Resolution change, inclusive of the use of different resolutions for different screen areas · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F13/4239

  with asynchronous protocol · CPC title