Modular periphery tile for integrated circuit device

Patent metadata

Field	Value
Publication number	US-10642946-B2
Application number	US-201816235933-A
Country	US
Kind code	B2
Filing date	Dec 28, 2018
Priority date	Dec 28, 2018
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

First claim

What is claimed is:

1. An integrated circuit system, comprising:
a first die comprising first programmable fabric circuitry; and
a second die comprising a first modular periphery intellectual property (IP) tile, wherein the first modular periphery IP tile comprises first circuitry configurable to perform a first function in association with the first programmable fabric circuitry, wherein the second die is communicatively coupled to the first die via a modular interface that is configurable to enable communication:
between the first die and the second die, when the first die is coupled to the second die via the modular interface;
between the first die and a third die, when the first die is coupled to the third die via the modular interface instead of the second die, wherein the third die comprises a second modular periphery intellectual property (IP) tile, wherein the second modular periphery IP tile comprises second circuitry configured to perform a second function in association with the first programmable fabric circuitry; and
between the second die and a fourth die, when the second die is coupled to the fourth die via the modular interface instead of the first die, wherein the fourth die comprises second programmable fabric circuitry, and wherein the first circuitry of the first modular periphery IP tile is configured to perform the first function in association with the second programmable fabric circuitry.

2. The integrated circuit system of claim 1 , wherein the first programmable fabric circuitry comprises field-programmable gate array (FPGA) circuitry.

3. The integrated circuit system of claim 1 , wherein the first modular periphery IP tile or the second modular periphery IP tile comprises a double data rate (DDR) tile, a low power DDR (LPDDR) tile, a high bandwidth memory (HBM) tile, embedded static random-access memory (eSRAM) tile, a Universal Interface Bus (UIB) tile, or an input/output (I/O) tile, or any combination thereof.

4. The integrated circuit system of claim 3 , wherein the modular interface comprises circuitry defined by a specification that enables communication over a silicon interposer to the double data rate (DDR) tile, the low power DDR (LPDDR) tile, the high bandwidth memory (HBM) tile, the embedded static random-access memory (eSRAM) tile, the Universal Interface Bus (UIB) tile, the input/output (I/O) tile, or any combination thereof to communicate data to and from the first programmable fabric circuitry.

5. The integrated circuit system of claim 1 , wherein the second die is configurable to bridge a configuration network-on-chip (CNOC) connection from the third die comprising additional programmable fabric circuitry to the second die, wherein the third die comprises a source of configuration.

6. The integrated circuit system of claim 1 , wherein the modular interface is configured to perform time divisional multiplexing (TDM).

7. The integrated circuit system of claim 6 , wherein the modular interface is configurable to facilitate direct communication between the first die and the second die, such that the integrated circuit system appears as a monolithic integrated circuit to a design software.

8. The integrated circuit system of claim 6 , wherein the modular interface is configured to support 2:1 time division multiplexing (TDM) between the first modular periphery IP tile and the first programmable fabric circuitry.

9. The integrated circuit system of claim 1 , wherein the first die comprises a first fabric network-on-chip (FNOC), and wherein the second die comprises a second fabric network-on-chip (FNOC).

10. The integrated circuit system of claim 9 , wherein the modular interface is configurable to bridge the first FNOC to the second FNOC.

11. The integrated circuit system of claim 9 , wherein the first FNOC and the second FNOC are configurable to facilitate high-speed, high-bandwidth communication between the first modular periphery IP tile and the first programmable fabric circuitry, between a plurality of programmable fabric circuitry, or any combination thereof.

12. An integrated circuit system, comprising:
a programmable fabric die comprising:
a first fabric network-on-chip (FNOC) configured to facilitate high-bandwidth communication, wherein the first FNOC comprises a network-on-chip (NOC) embedded within the programmable fabric die; and
a first direct interface column configured to facilitate direct communication without interfacing via the first FNOC, wherein the first direct interface column comprises a time division multiplexing (TDM) interface;

a modularized periphery intellectual property (IP) tile communicatively coupled to the programmable fabric die, wherein the modularized periphery IP tile comprises:
a second FNOC configured to facilitate high-bandwidth communication with the programmable fabric die by interfacing with second FNOC; and
a second direct interface column configured to facilitate direct communication with the programmable fabric die by interfacing with the first direct interface column without interfacing via the second FNOC, wherein the second direct interface column comprises the TDM interface.

13. The integrated circuit system of claim 12 , wherein the second FNOC is configured to facilitate communication with the programmable fabric die by interfacing with second FNOC via edge interface columns.

14. The integrated circuit system of claim 12 , wherein the modularized periphery IP tile comprises a plurality of modular IO blocks, each IO block comprising direct interface columns.

15. The integrated circuit system of claim 12 , wherein the modularized periphery IP tile comprises a Universal Interface Bus (UIB) tile configured to interface a high bandwidth memory (HBM) IP.

16. The integrated circuit system of claim 15 , wherein the UIB tile facilitates bridging a configuration network-on-chip (CNOC) connection from an additional programmable fabric die to the programmable fabric die, wherein the additional programmable fabric die comprises a source of configuration.

17. The integrated circuit system of claim 12 , comprising at least one additional programmable fabric die, wherein the at least one additional programmable fabric die is communicatively coupled to the programmable fabric die via at least one direct interface column and the first FNOC.

Assignees

• Intel Corp

Inventors

• Teh Chee Hak
• Nalamalpu Ankireddy
• Hossain Md Altaf
• Subbareddy Dheeraj
• Atsatt Sean R
• Tang Lai Guan

Classifications

• H03K19/17744

  for input/output signals · CPC title

• H03K19/17796

  for physical disposition of blocks · CPC title

• H04L12/43

  with synchronous transmission, e.g. time division multiplex [TDM], slotted rings · CPC title

• G06F15/7825

  Globally asynchronous, locally synchronous, e.g. network on chip · CPC title

• G06F30/34 Primary

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title