Current balancing, current sensor, and phase balancing apparatus and method for a voltage regulator

Patent metadata

Field	Value
Publication number	US-10641799-B2
Application number	US-201916254468-A
Country	US
Kind code	B2
Filing date	Jan 22, 2019
Priority date	Mar 15, 2013
Publication date	May 5, 2020
Grant date	May 5, 2020

Abstract

Apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), and compensator for a voltage regulator (VR), are provided. In one example, an apparatus includes: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.

First claim

We claim:

1. An apparatus comprising:
a first p-type transistor coupled to a power supply rail to provide an input power supply voltage and current, wherein the first p-type transistor is controlled by a first switchable signal;
a second p-type transistor coupled in series with the first p-type transistor, wherein the second p-type transistor is biased by a first bias;
a first n-type transistor coupled in series with the second p-type transistor, wherein the first n-type transistor is biased by a second bias;
a second n-type transistor coupled to series with the first n-type transistor, wherein the second p-type transistor is controlled by a second switchable signal, and wherein the a second n-type transistor is coupled to ground;
a plurality of drivers to drive pulse width modulated (PWM) signals as the first and second switchable signals; and
a modulator to generate one or more PWM signals as input to the plurality of drivers.

2. The apparatus of claim 1 , wherein the first and second biases are a function of the input power supply voltage.

3. The apparatus of claim 1 comprises:
a first current sensor to sense current through the first p-type transistor; and
a second current sensor to sense current through the first n-type transistor.

4. The apparatus of claim 3 , wherein the first and second current sensors include a common gate amplifier.

5. The apparatus of claim 3 , wherein the first current sensor comprises:
a third p-type transistor coupled to the input power supply rail, wherein a gate of the third p-type transistor is coupled to a drain of the first p-type transistor;
a fourth p-type transistor coupled in series with the third p-type transistor, wherein a gate of the fourth p-type transistor is controllable by the first switchable signal; and
a fifth p-type transistor coupled in series with the fourth p-type transistor, wherein a gate of the fifth p-type transistor is controllable by the first bias.

6. The apparatus of claim 5 , comprises first and second current mirrors, wherein the first current sensor comprises:
a sixth p-type transistor coupled to the input power supply rail, wherein a gate of the sixth p-type transistor is coupled to a drain of the first p-type transistor, and wherein drain terminals of the third and sixth p-type transistors are coupled to the first and second current mirrors.

7. The apparatus of claim 6 comprises:
seventh p-type transistor coupled in series with the sixth p-type transistor, wherein a gate of the seventh p-type transistor is controllable by the first switchable signal; and
an eighth p-type transistor coupled in series with the seventh p-type transistor, wherein a gate of the eighth p-type transistor is controllable by the first bias, and wherein the eighth p-type transistor is coupled to the power supply rail.

8. The apparatus of claim 5 , wherein the second current sensor comprises:
a third n-type transistor coupled in series with the fifth p-type transistor, wherein a gate of the third n-type transistor is controllable by the second bias;
a fourth n-type transistor coupled in series with the third n-type transistor, wherein a gate of the fourth n-type transistor is controllable by the second switchable signal; and
a fifth n-type transistor coupled in series with the fourth n-type transistor, wherein a gate of the fifth p-type transistor is controllable by a source of the first n-type transistor.

9. The apparatus of claim 8 , comprises third and fourth current mirrors, wherein the second current sensor comprises:
a sixth n-type transistor coupled to ground, and wherein a gate of the sixth n-type transistor is coupled to the second bias.

10. The apparatus of claim 9 comprises:
seventh n-type transistor coupled in series with the sixth n-type transistor, wherein a gate of the seventh n-type transistor is controllable by the second switchable signal; and
an eighth n-type transistor coupled in series with the seventh n-type transistor, wherein a gate of the eighth n-type transistor is controllable by the source of the first n-type transistor, wherein the eighth n-type transistor is coupled to ground, and wherein drain terminals of the seventh and eighth n-type transistors are coupled to the third and fourth current mirrors.

11. An apparatus comprising:
a first current sensor coupled to an input power supply rail and to a high-side switch of a DC-DC converter;
a second current sensor coupled to ground and to a low-side switch of the DC-DC converter, wherein the high-side switch is coupled in series with the low-side switch;
an n-type transistor coupled in series with the first current sensor; and
a p-type transistor coupled in series with the n-type transistor and the second current sensor.

12. The apparatus of claim 11 , wherein the n-type transistor is a first n-type transistor, wherein the apparatus comprises a second n-type transistor, and wherein a gate of the first n-type transistor is coupled to a gate of the second n-type transistor.

13. The apparatus of claim 12 , wherein the p-type transistor is a first p-type transistor, wherein the apparatus comprises a second p-type transistor, and wherein a gate of the first p-type transistor is coupled to a gate of the second p-type transistor.

14. The apparatus of claim 13 , wherein the second p-type transistor and the second n-type transistor are coupled in series.

15. The apparatus of claim 13 comprises a unity gain amplifier coupled to the second n-type transistor and the second p-type transistor.

16. The apparatus of claim 12 , wherein the second n-type transistor is coupled to a current mirror.

17. A system comprising:
a processor core;
a DC-DC converter to provide a regulated power supply to the processor core, wherein the DC-DC converter comprises:
a first current sensor coupled to an input power supply rail and to a high-side switch of a DC-DC converter;
a second current sensor coupled to ground and to a low-side switch of the DC-DC converter, wherein the high-side switch is coupled in series with the low-side switch;
an n-type transistor coupled in series with the first current sensor; and
a p-type transistor coupled in series with the n-type transistor and the second current sensor; and

an inductor coupled to the high-side and low-side switches of the DC-DC converter;
a capacitor coupled to the inductor, wherein the inductor is coupled to the processor core; and
a wireless interface to allow the processor core to communicate with another device.

18. The system of claim 17 , wherein the n-type transistor is a first n-type transistor, wherein the apparatus comprises a second n-type transistor, and wherein a gate of the first n-type transistor is coupled to a gate of the second n-type transistor.

19. The system of claim 18 , wherein the p-type transistor is a first p-type transistor, wherein the apparatus comprises a second p-type transistor, wherein a gate of the first p-type transistor is coupled to a gate of the second p-type transistor, and wherein the second p-type transistor and the second n-type transistor are coupled together in series.

20. The system of claim 19 comprises a unity gain amplifier coupled to the second n-type transistor and the second p-type transistor, wherein the second n-type transistor is coupled to a current mirror.

Assignees

• Intel Corp

Inventors

• Schrom Gerhard
• Hodgson J Keith
• Lyakhov Alexander
• Tang Chiu Keung
• Raghuraman Narayanan
• Natarajan Narayanan

Classifications

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M3/157 Primary

  with digital control · CPC title

• H03L5/00

  Automatic control of voltage, current, or power · CPC title

• H03M1/685

  the quantisation value generators of both converters being arranged in a common two-dimensional array · CPC title

• H02M3/156 Primary

  with automatic control of output voltage or current, e.g. switching regulators · CPC title