Broadband frequency tripler

Patent metadata

Field	Value
Publication number	US-10637450-B2
Application number	US-201716476318-A
Country	US
Kind code	B2
Filing date	Feb 3, 2017
Priority date	Feb 3, 2017
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

A frequency multiplier ( 200 ) generates an output signal with a frequency 3 times of the input signal frequency. The frequency multiplier ( 200 ) comprises four cascaded stages. A first stage ( 201 ) is configured to receive an input signal and generate harmonics signals of the input signal. A second stage ( 202 ) is a passive filter, a frequency response of the passive filter has either a peak or a dip around an upper frequency end of a frequency band of the input signal. A third stage ( 203 ) is configured to mix the 1st and the 2nd order harmonics signals to generate 3rd order harmonic signals. A fourth stage ( 204 ) is configured to suppress the 1st and even-order harmonics signals and output a signal dominated with a frequency 3 times of the input signal frequency.

First claim

The invention claimed is:

1. A frequency multiplier for generating an output signal from an input signal, wherein a frequency of the output signal is three times a frequency of the input signal, the frequency multiplier comprising:
a first stage configured to receive an input signal and generate harmonics signals of the input signal;
a second stage comprising a passive filter, wherein a frequency response of the passive filter has either a peak or a dip around an upper frequency end of a frequency band of the input signal such that, at outputs of the second stage:
either a power of the first order harmonic signal increases and a power of the second order harmonic signal decreases when the input signal frequency increases; or
a power of the first order harmonic signal decreases and a power of the second order harmonic signal increases when the input signal frequency increases;

a third stage configured to mix the first and second order harmonics signals to generate third order harmonic signals; and
a fourth stage configured to suppress the first and even-order harmonics signals and output a signal dominated with a frequency three times the input signal frequency.

2. The frequency multiplier of claim 1 , wherein the first stage comprises a common-emitter configured transistor pair having two inputs to receive a differential input signal and two outputs to generate harmonics signals for the second stage.

3. The frequency multiplier of claim 1 :
wherein the passive filter comprises two identical filters each being connected to one output of the first stage;
wherein each filter comprises a first inductor or transmission line and a second inductor or transmission line connected in series with a capacitor; wherein one terminal of the first inductor is connected with one terminal of the second inductor and to one output of the first stage, wherein another terminal of the first inductor is connected to a voltage supplier, wherein one terminal of the capacitor is an output of the filter.

4. The frequency multiplier of claim 1 :
wherein the third stage comprises a common-emitter configured transistor pair acting as a trans-conductance mixer to mix the first and second order harmonics signals; and
wherein the common-emitter configured transistor pair has two inputs to receive signals from the second stage and two outputs to provide mixed signals to the fourth stage.

5. The frequency multiplier of claim 1 :
wherein the fourth stage comprises two coupled transmission lines;
wherein two terminals on opposite sides of the coupled transmission lines are connected to the two outputs of the third stage respectively;
wherein two another terminals of the coupled transmission lines are connected to a voltage supplier.

6. The frequency multiplier of claim 5 , wherein the fourth stage comprises a capacitor and inductor or transmission line network configured to suppress the first order harmonic signal and for impedance matching.

7. The frequency multiplier of claim 1 , further comprising a balun configured to transfer a single-ended input signal into a differential signal to input to the first stage.

8. A multi-band transceiver, comprising:
a frequency multiplier for generating an output signal from an input signal, wherein a frequency of the output signal is three times a frequency of the input signal, the frequency multiplier comprising:
a first stage configured to receive an input signal and generate harmonics signals of the input signal;
a second stage comprising a passive filter, wherein a frequency response of the passive filter has either a peak or a dip around an upper frequency end of a frequency band of the input signal such that, at outputs of the second stage:
either a power of the first order harmonic signal increases and a power of the second order harmonic signal decreases when the input signal frequency increases; or
a power of the first order harmonic signal decreases and a power of the second order harmonic signal increases when the input signal frequency increases;

a third stage configured to mix the first and second order harmonics signals to generate third order harmonic signals; and
a fourth stage configured to suppress the first and even-order harmonics signals and output a signal dominated with a frequency three times the input signal frequency.

9. An electronic device, comprising:
a frequency multiplier for generating an output signal from an input signal, wherein a frequency of the output signal is three times a frequency of the input signal, the frequency multiplier comprising:
a first stage configured to receive an input signal and generate harmonics signals of the input signal;
a second stage comprising a passive filter, wherein a frequency response of the passive filter has either a peak or a dip around an upper frequency end of a frequency band of the input signal such that, at outputs of the second stage:
either a power of the first order harmonic signal increases and a power of the second order harmonic signal decreases when the input signal frequency increases; or
a power of the first order harmonic signal decreases and a power of the second order harmonic signal increases when the input signal frequency increases;

a third stage configured to mix the first and second order harmonics signals to generate third order harmonic signals; and
a fourth stage configured to suppress the first and even-order harmonics signals and output a signal dominated with a frequency three times the input signal frequency.

10. A method in a frequency multiplier for generating an output signal with a frequency three times a frequency of an input signal, the method comprising:
generating harmonics signals of the input signal in a first stage by a common-emitter configured transistor pair;
shaping the generated harmonics signals in a second stage such that, at outputs of the second stage:
either a power of the first order harmonic signal decreases and a power of the second order harmonic signal increases when the input signal frequency increases; or
a power of the first order harmonic signal increases and a power of the second order harmonic signal decreases when the input signal frequency increases;

mixing first and the second order harmonics signals to generate third order harmonic signals in a third stage by a trans-conductance mixer comprising a common-emitter configured transistor pair; and
suppressing the first and even-order harmonics signals in a fourth stage by two coupled transmission lines and a capacitor and inductor network.

Assignees

• Ericsson Telefon Ab L M

Inventors

• Bao Mingquan

Classifications

• H04B1/40

  Circuits · CPC title

• H03K5/00006 Primary

  Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68) · CPC title

• H03B19/14 Primary

  by means of a semiconductor device · CPC title

• H03H7/383

  comprising distributed impedance elements together with lumped impedance elements · CPC title

• H03H7/0123

  comprising distributed impedance elements together with lumped impedance elements · CPC title