Power amplifier apparatus, envelope tracking amplifier apparatus and method of amplifying a signal

Patent metadata

Field	Value
Publication number	US-10637404-B2
Application number	US-201515778749-A
Country	US
Kind code	B2
Filing date	Dec 17, 2015
Priority date	Dec 17, 2015
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

An amplifier apparatus ( 332 ) comprises a main linear amplifier sub-circuit ( 402 ) having a main driving signal input terminal ( 331 ) and a main amplifier output terminal ( 406 ). The apparatus also comprises an auxiliary linear amplifier sub-circuit ( 404 ) having an auxiliary driving signal input terminal ( 357 ) and an auxiliary amplifier output terminal ( 408 ). A combining network ( 410 ) is operably coupled between the main amplifier output terminal ( 406 ) and the auxiliary amplifier output terminal ( 408 ), the combining network ( 410 ) having a main-side terminal ( 424 ) and an auxiliary-side terminal ( 434 ). The main linear amplifier sub-circuit ( 402 ) is arranged to generate, when in use, a main amplified signal in response to a main driving signal applied at the main driving signal input terminal ( 331 ). The auxiliary linear amplifier sub-circuit ( 404 ) is arranged to generate, when in use, an impedance modifying signal at the auxiliary-side terminal ( 357 ) in response to an auxiliary driving signal and at substantially the same time as the main linear amplifier sub-circuit ( 402 ) generates the main amplified signal, the auxiliary linear amplifier sub-circuit ( 404 ) also being arranged to amplify substantially more than half of each wave cycle of the auxiliary driving signal.

First claim

The invention claimed is:

1. An amplifier apparatus comprising:
a main linear amplifier sub-circuit having a main driving signal input terminal and a main amplifier output terminal;
an auxiliary linear amplifier sub-circuit having an auxiliary driving signal input terminal and an auxiliary amplifier output terminal;
a combining network operably coupled between the main amplifier output terminal and the auxiliary amplifier output terminal, the combining network having a main-side terminal and an auxiliary-side terminal; wherein
the main linear amplifier sub-circuit is arranged to generate, when in use, a main amplified signal in response to a main driving signal applied at the main driving signal input terminal; and
the auxiliary linear amplifier sub-circuit is arranged to generate, when in use, an impedance modifying signal at the auxiliary-side terminal in response to an auxiliary driving signal and at substantially the same time as the main linear amplifier sub-circuit generates the main amplified signal, the auxiliary linear amplifier sub-circuit also being arranged to amplify substantially more than half of each wave cycle of the auxiliary driving signal.

2. The apparatus according to claim 1 , wherein the auxiliary linear amplifier sub-circuit is arranged to generate, when in use, the impedance modifying signal in response to the auxiliary driving signal being related to the main driving signal by a complex scaling factor so as to modify an impedance presented to the main linear amplifier sub-circuit, thereby maximising electrical power transfer from the main amplifier output terminal.

3. The apparatus according to claim 1 , wherein the impedance modifying signal is generated to modify an impedance value at the auxiliary-side terminal in order to maintain a predetermined load impedance value presented to the main linear amplifier sub-circuit.

4. The apparatus according to claim 1 , wherein the combining network is an admittance inverter.

5. The apparatus according to claim 4 , wherein the admittance inverter is a π-network of frequency invariant susceptances.

6. The apparatus according to claim 1 , wherein the combining network is a quadrature hybrid junction.

7. The apparatus according to claim 1 , further comprising:
a driving signal generator operably coupled to the auxiliary linear amplifier sub-circuit.

8. The apparatus according to claim 7 , when dependent upon claim 2 , wherein the driving signal generator is arranged to generate the auxiliary driving signal by application of the complex scaling factor.

9. The apparatus according to claim 8 , wherein the application of the complex scaling factor is a digital signal processing operation.

10. A radio frequency processing resource comprising:
an amplifier apparatus according to claim 1 .

11. A communications apparatus comprising:
the radio frequency processing resource according to claim 10 ; and
a load operably coupled to the auxiliary-side terminal of the combining network.

12. The apparatus according to claim 11 , wherein the impedance modifying signal applied at the auxiliary-side terminal is arranged to modify an impedance value of the load with respect to the main linear amplifier sub-circuit, thereby maximising power transfer from the main linear amplifier sub-circuit into the load.

13. A communications apparatus comprising:
a radio frequency processing resource, the radio frequency processing resource comprising an amplifier apparatus according to claim 2 ;
a load operably coupled to the auxiliary-side terminal of the combining network;
a baseband processing resource comprising a main signal path and an auxiliary signal path; wherein
the main signal path and the auxiliary signal path are respectively coupled to a common transmit signal source; and
the complex scaling factor is applied in the auxiliary signal path.

14. A communications apparatus comprising:
a radio frequency processing resource, the radio frequency processing resource comprising an amplifier apparatus according to claim 2 ;
a load operably coupled to the auxiliary-side terminal of the combining network; wherein
the complex scaling factor, α, is:

α
=

-

j
⁡

(

kZ
0

-

Y
I

k

)

where Z 0 is an impedance value of the load to be presented to the main linear amplifier sub-circuit, k is susceptance value of each individual susceptance of the π-network of frequency invariant susceptances, and Y l is an admittance value of the load.

15. An envelope tracking amplifier apparatus comprising:
the power amplifier apparatus according to claim 8 ; and
an envelope response processor arranged to control bias of the main linear amplifier sub-circuit and to generate the complex scaling factor.

16. The apparatus according to claim 15 , wherein the envelope response processor comprises:
a bias shaper; and
an impedance shaper.

17. The apparatus according to claim 16 , wherein the envelope response processor comprises:
an envelope detector arranged to generate, when in use, an envelope detection signal; and
the bias shaper is arranged to receive the envelope detection signal and to generate a bias network control signal in response to the envelope detection signal.

18. The apparatus according to claim 17 , wherein the main linear amplifier sub-circuit comprises a bias network circuit, the bias network circuit being operably coupled to the bias shaper.

19. The apparatus according to claim 16 , wherein the envelope response processor comprises:
an envelope detector arranged to generate, when in use, an envelope detection signal, the apparatus further comprising:
a signal scaling module; wherein
the impedance shaper is arranged to receive the envelope detection signal and to cooperate with the signal scaling module in order to generate the complex scaling factor in response to the envelope detection signal and knowledge of an impedance of the combining network.

20. A method of amplifying a main drive signal, the method comprising:
providing a main amplifier sub-circuit having a main driving signal input terminal and a main amplifier output terminal;
providing an auxiliary amplifier sub-circuit having an auxiliary driving signal input terminal and an auxiliary amplifier output terminal;
operably coupling a combining network between the main amplifier output terminal and the auxiliary amplifier output terminal;
applying the main driving signal to the main driving signal input terminal, the main linear amplifier sub-circuit generating a main amplified signal in response to the main driving signal;
applying an auxiliary driving signal to the auxiliary driving signal input terminal, the auxiliary linear amplifier sub-circuit generating an impedance modifying signal in response to the auxiliary driving signal and at substantially the same time as the main linear amplifier sub-circuit; and
the auxil

Assignees

• Ublox Ag

Inventors

• Haine John

Classifications

• H03F2203/21142

  Output signals of a plurality of power amplifiers are parallel combined to a common output · CPC title

• H03F3/211

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title

• H03F3/602

  Combinations of several amplifiers · CPC title

• H03F2200/102

  A non-specified detector of a signal envelope being used in an amplifying circuit · CPC title

• H03F3/604

  using FET's · CPC title