Ramp offset compensation circuit in a buck boost converter

Patent metadata

Field	Value
Publication number	US-10637357-B1
Application number	US-201816226400-A
Country	US
Kind code	B1
Filing date	Dec 19, 2018
Priority date	Dec 20, 2017
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

A converter includes a buck boost converter circuit to generate an output voltage in response to an input voltage, and an inductor current compensation circuit to generate an output current compensated inductor current signal corresponding to a sensed input current. The output current compensated inductor current signal includes a voltage gap between a boost ramp valley and a buck ramp peak. The buck boost converter circuit includes a current sensor to receive the input voltage, the current sensor to sense an input current corresponding to the input voltage, an upper buck transistor coupled to the input voltage node, an upper boost transistor coupled to an output voltage node to output the output voltage, and an inductor coupled between the upper buck transistor and the upper boost transistor. The inductor current compensation circuit adjusts the voltage gap based on an offset compensation voltage corresponding to a switching frequency.

First claim

What is claimed is:

1. A converter, comprising:
a buck boost converter circuit configured to generate an output voltage in response to an input voltage, the buck boost converter circuit comprising:
a current sensor coupled to an input voltage node configured to receive the input voltage, the current sensor configured to sense an input current corresponding to the input voltage;
an upper buck transistor coupled to the input voltage node;
an upper boost transistor coupled to an output voltage node, the output voltage node configured to output the output voltage; and
an inductor coupled between the upper buck transistor and the upper boost transistor; and

an inductor current compensation circuit configured to generate an output current compensated inductor current signal corresponding to the sensed input current, the output current compensated inductor current signal including a voltage gap between a boost ramp valley and a buck ramp peak,
wherein the inductor current compensation circuit is configured to adjust the voltage gap based on an offset compensation voltage corresponding to a switching frequency.

2. The converter of claim 1 , wherein the inductor current compensation circuit comprises:
a boost ramp offset compensation circuit configured to generate the offset compensation voltage corresponding to the switching frequency; and
a boost ramp generation circuit configured to generate a boost ramp of the output current compensated inductor current signal corresponding to the offset compensation voltage.

3. The converter of claim 2 , wherein the boost ramp offset compensation circuit comprises a current mirror coupled to a current source configured to generate a current corresponding to the switching frequency, the current mirror configured to generate a mirrored current corresponding to the current generated by the current source.

4. The converter of claim 3 , wherein the boost ramp offset compensation circuit further comprises a resistor coupled to receive the mirrored current from the current mirror, the resistor configured to generate a boost side adjustment voltage corresponding to the mirrored current.

5. The converter of claim 4 , wherein the boost ramp offset compensation circuit further comprises an amplifier coupled to the resistor, the amplifier configured to generate the offset compensation voltage corresponding to the boost side adjustment voltage and to provide the offset compensation voltage to the boost ramp generation circuit.

6. The converter of claim 5 , wherein parameters of the current mirror, the resistor, and the amplifier correspond proportionally to a total minimum on and off time in a boost cycle or a buck cycle.

7. The converter of claim 1 , further comprising a mode control logic circuit configured to generate a mode control signal to control an operation mode of the buck boost converter circuit to operate in one of a buck mode, a boost mode, and a buck-boost mode,
wherein the inductor current compensation circuit is configured to adjust a boost ramp based on the offset compensation voltage corresponding to the switching frequency when the mode control signal indicates a boost cycle within the buck-boost mode.

8. An inductor current compensation circuit configured to generate an output current compensated inductor current signal corresponding to a sensed input current provided by a buck boost converter, the inductor current compensation circuit comprising:
a boost ramp offset compensation circuit configured to generate an offset compensation voltage corresponding to a switching frequency; and
a boost ramp generation circuit configured to generate a boost ramp of the output current compensated inductor current signal corresponding to the offset compensation voltage,
wherein the inductor current compensation circuit is configured to generate the output current compensated inductor current signal having a voltage gap between a boost ramp valley and a buck ramp peak, and to adjust the voltage gap based on the offset compensation voltage corresponding to the switching frequency.

9. The circuit of claim 8 , wherein the boost ramp offset compensation circuit comprises a current mirror coupled to a current source configured to generate a current corresponding to the switching frequency, the current mirror configured to generate a mirrored current corresponding to the current generated by the current source.

10. The circuit of claim 9 , wherein the boost ramp offset compensation circuit further comprises a resistor coupled to receive the mirrored current from the current mirror, the resistor configured to generate a boost side adjustment voltage corresponding to the mirrored current.

11. The circuit of claim 10 , wherein the boost ramp offset compensation circuit further comprises an amplifier coupled to the resistor, the amplifier configured to generate the offset compensation voltage corresponding to the boost side adjustment voltage and to provide the offset compensation voltage to the boost ramp generation circuit.

12. The circuit of claim 11 , wherein parameters of the current mirror, the resistor, and the amplifier correspond proportionally to a total minimum on and off time in a boost cycle or a buck cycle.

13. The circuit of claim 8 , wherein the inductor current compensation circuit is configured to adjust a boost ramp based on the offset compensation voltage corresponding to the switching frequency when a mode control signal received from a mode control logic circuit indicates a boost cycle within a buck-boost mode.

14. A method for generating an output current compensated inductor current signal corresponding to a sensed input current provided by a buck boost converter circuit configured to generate an output voltage in response to an input voltage, the method comprising:
receiving, from the buck boost converter circuit, the sensed input current corresponding to the input voltage; and
generating the output current compensated inductor current signal corresponding to the sensed input current, the output current compensated inductor current signal having a voltage gap between a boost ramp valley and a buck ramp peak,
wherein the voltage gap is adjusted based on a boost ramp offset compensation voltage corresponding to a switching frequency.

15. The method of claim 14 , further comprising: generating a boost ramp of the output current compensated inductor current signal corresponding to the boost ramp offset compensation voltage.

16. The method of claim 15 , further comprising:
generating a current corresponding to the switching frequency; and
generating a mirrored current based on the current corresponding to the switching frequency.

17. The method of claim 16 , further comprising: generating a boost side adjustment voltage corresponding to the mirrored current.

18. The method of claim 17 , further comprising:
generating the boost ramp offset compensation voltage based on the boost side adjustment voltage; and
adjusting the boost ramp of the output current compensated inductor current signal corresponding to the boost ramp offset compensation voltage to generate the voltage gap.

19. The method of claim 18 , further comprising: selecting parameters of a current mirror for generating the mirrored current, a resistor for generating the boost side adjustment voltage, and an amplifier for generating the boost ramp offset compensation voltage to proportionally correspond to a total minimum on and off time in a boost cycle or a buck cycle.

20. The method of claim 14 , further c

Assignees

• Renesas Electronics America Inc

Inventors

• Zhan Xiaodong
• Singh Prabhjot
• Yu Long

Classifications

• G05F1/62 Primary

  using bucking or boosting DC sources · CPC title

• H02M3/157

  with digital control · CPC title

• H02M3/1582 Primary

  Buck-boost converters (H02M3/1584 takes precedence) · CPC title

• H02M2001/0032

  Electricity · mapped topic

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title