Power factor correction circuit and driving method thereof

Patent metadata

Field	Value
Publication number	US-10637350-B2
Application number	US-201815901228-A
Country	US
Kind code	B2
Filing date	Feb 21, 2018
Priority date	Mar 23, 2015
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

A power factor correction circuit corrects a filter current flowing through a filter capacitor asymmetrically based on a peak of an input voltage by controlling a switching operation of a power switch, thereby correcting distortion of an input current.

First claim

What is claimed is:

1. A power factor correction circuit comprising:
adjustment signal generator that is configured to receive an input detection voltage that corresponds to an input voltage of a power supply and to generate an adjustment signal, the adjustment signal having a waveform that is asymmetric relative to a peak of a full-wave rectified waveform of the input voltage; and
a duty generator that is configured to turn on a power switch of the power supply in accordance with a clock signal, to generate a compensation signal by comparing a feedback signal with a reference signal, to generate an adjusted compensation signal by adjusting the compensation signal using the adjustment signal, and to turn off the power switch in response to the adjusted compensation signal, the adjusted compensation signal being a delayed version of the compensation signal,
wherein the duty generator comprises a time compensator that is configured to generate the adjusted compensation signal by delaying the compensation signal by a sum of a compensation period and at least one switching cycle of the power switch, the compensation period being determined based on the adjustment signal.

2. The power factor correction circuit of claim 1 , wherein the adjustment signal generator is configured to generate the adjustment signal by differentiating the input voltage.

3. The power factor correction circuit of claim 1 , wherein the feedback signal corresponds to an output voltage of the power supply, the reference signal is a sawtooth wave signal, and the duty generator comprises:
a feedback generator that is configured to generate the feedback signal; and
a sawtooth wave generator that is configured to generate the sawtooth wave signal,
wherein the duty generator is configured to generate the adjusted compensation signal by comparing the feedback signal to the sawtooth wave signal.

4. The power factor correction circuit of claim 3 , wherein the feedback generator is configured to generate the feedback signal by adding the adjustment signal to an error signal corresponding to an error between the output voltage of the power supply and a reference voltage.

5. The power factor correction circuit of claim 3 , wherein the sawtooth wave generator is configured to adjust a slope of the sawtooth wave signal according to the adjustment signal.

6. The power factor correction circuit of claim 3 , wherein the sawtooth wave generator is configured to increase from a level according to the adjustment signal.

7. The power factor correction circuit of claim 3 , wherein the duty generator further comprises a time compensator that is configured to delay the adjusted compensation signal according to the adjustment signal.

8. The power factor correction circuit of claim 1 , wherein the reference signal corresponds to a current through the power switch, and the duty generator is configured to generate the adjusted compensation signal by adding the adjustment signal to the feedback signal.

9. The power factor correction circuit of claim 1 , wherein the duty generator comprises:
a feedback generator that is configured to generate the feedback signal; and
a sensing voltage compensator that is configured to generate the reference signal by adjusting a sense voltage that corresponds to a current through the power switch using the adjustment signal.

10. The power factor correction circuit of claim 1 , wherein the adjustment signal increases throughout a cycle of the input detection voltage.

11. A method of operation of a power factor correction circuit, the method comprising:
receiving an input detection voltage that corresponds to an input voltage of a power supply;
generating an adjustment signal having a waveform that is asymmetric relative to a peak of a full-wave rectified waveform of the input voltage;
turning on a power switch of the power supply in accordance with a clock signal;
generating a compensation signal by comparing a feedback signal with a reference signal;
generating an adjusted compensation signal by delaying the compensation signal by a sum of a compensation period and at least one switching cycle of the power switch, the compensation period being determined based on the adjustment signal; and
turning off the power switch in response to the adjusted compensation signal.

12. The method of claim 11 , wherein generating the adjustment signal comprises:
generating a differentiated voltage by differentiating the input voltage.

13. The method of claim 11 , wherein the feedback signal corresponds to an output voltage of the power supply, the reference signal is a sawtooth wave signal, and the method further comprises:
generating the feedback signal by adding the adjustment signal to an error signal corresponding to an error between the output voltage of the power supply and a reference voltage; and
comparing the feedback signal to the sawtooth wave signal to generate the adjusted compensation signal.

14. The method of claim 11 , wherein the feedback signal corresponds to an output voltage of the power supply, the reference signal is a sawtooth wave signal, and the method further comprises:
adjusting the sawtooth wave signal according to the adjustment signal.

15. The method of claim 11 , wherein the reference signal corresponds to a current through the power switch, and the adjusted compensation signal is generated by adding the adjustment signal to the feedback signal.

16. The method of claim 11 , further comprising:
generating a sense voltage that corresponds to a current through the power switch; and
generating the reference signal by adjusting the sense voltage according to the adjustment signal.

17. A power factor correction circuit comprising:
a differentiator that is configured to receive an input detection voltage that corresponds to an input voltage of a power supply and to differentiate the input detection voltage to generate a differentiated signal; and
a duty generator that is configured to receive an adjustment signal that is based on the differentiated signal, to generate a compensation signal by comparing a feedback signal with a reference signal, to generate an adjusted compensation signal by adjusting the compensation signal using the adjustment signal, and to turn off the power switch in response to the adjusted compensation signal, the adjusted compensation signal being a delayed version of the compensation signal,
wherein the duty generator comprises a time compensator that is configured to generate the adjusted compensation signal by delaying the compensation signal by a sum of a compensation period and at least one switching cycle of the power switch, the compensation period being determined based on the adjustment signal.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Eum Hyun-Chul
• Kim Taesung
• Park In-Ki
• Kim Young-Jong

Classifications

• H02M1/12

  Arrangements for reducing harmonics from AC input or output · CPC title

• H02M3/33523

  with galvanic isolation between input and output of both the power stage and the feedback loop · CPC title

• H02M1/4258 Primary

  using a single converter stage both for correction of AC input power factor and generation of a regulated and galvanically isolated DC output voltage (H02M1/4241 takes precedence) · CPC title

• Y02B70/126

  Cross-Sectional Technologies · mapped topic

• H02M2001/0025

  Electricity · mapped topic