Semiconductor chip and method for forming a chip pad

Patent metadata

Field	Value
Publication number	US-10636754-B2
Application number	US-201916262530-A
Country	US
Kind code	B2
Filing date	Jan 30, 2019
Priority date	Jul 28, 2014
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

A semiconductor chip with different chip pads and a method for forming a semiconductor chip with different chip pads are disclosed. In some embodiments, a semiconductor chip includes a chip front side, a first chip pad located on the chip front side, a second chip pad located on the chip front side and an electrically insulating material located between the first chip pad and the second chip pad, wherein the first chip pad includes a surface layer predominantly comprising copper and the second chip pad includes a surface layer predominantly comprising aluminum.

First claim

What is claimed is:

1. A semiconductor chip comprising:
a chip front side;
an aluminum layer comprising predominately aluminum directly located on the chip front side, wherein the aluminum layer has a first region and a second region, and wherein the second region is laterally spaced apart from the first region;
an electrically insulating material located between the first and second regions of the aluminum layer;
a tungsten barrier layer comprising predominantly tungsten directly located on the first region of the aluminum layer but not on the second region of the aluminum layer; and
a copper layer comprising predominantly copper directly located on the tungsten barrier layer so that the first region of the aluminum layer, the tungsten barrier layer and the copper layer form a first chip pad with the copper layer as a surface layer of the first chip pad and the second region of the aluminum layer forms a second chip pad with the aluminum layer as a surface layer of the second chip pad.

2. The semiconductor chip of claim 1 , wherein the tungsten barrier layer has a tungsten content ranging from 60% to 90%.

3. The semiconductor chip of claim 1 , wherein the tungsten barrier layer is a titanium tungsten barrier layer consisting essentially of titanium and tungsten.

4. The semiconductor chip of claim 3 , wherein the titanium tungsten barrier layer has a composition of Ti0.2W0.8.

5. The semiconductor chip of claim 1 , wherein the surface layer of the second chip pad consists essentially of aluminum.

6. The semiconductor chip of claim 1 , wherein the surface layer of the first chip pad consists essentially of copper.

7. The semiconductor chip of claim 1 , further comprising a soldering material in contact with the surface layer of the first chip pad.

8. The semiconductor chip of claim 7 , further comprising a bond wire joined to the surface layer of the second chip pad.

Assignees

• Infineon Technologies Ag

Inventors

• Kramp Stefan
• Koitz Marco

Classifications

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H01L2224/05124

  Electricity · mapped topic

• H01L24/13

  Electricity · mapped topic

• H01L2224/45144

  Electricity · mapped topic