Host controller apparatus, host controller device, and method for a host controller for determining information related to a time shift for transmitting instructions on a command and address bus, host controller and computer system

Patent metadata

Field	Value
Publication number	US-10635628-B2
Application number	US-201816023150-A
Country	US
Kind code	B2
Filing date	Jun 29, 2018
Priority date	Jun 29, 2018
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

A host controller apparatus for determining information related to a time shift for transmitting instructions on a command and address bus includes an interface for transmitting a plurality of instruction signals to a memory module via the command and address bus and for receiving a loopback feedback signal from the memory module. The host controller apparatus further includes a control module configured to transmit the plurality of instruction signals to the memory module via the command and address bus. The control module is configured to receive the loopback feedback signal from the memory module. The loopback feedback signal includes a looped-back composite version of the plurality of instruction signals. The control module is configured to determine the information related to the time shift for transmitting instructions on the command and address bus based on the loopback feedback signal.

First claim

What is claimed is:

1. A host controller apparatus for determining information related to a time shift for transmitting instructions on a command and address bus, the host controller apparatus comprising
an interface for transmitting a plurality of instruction signals to a memory module via the command and address bus and for receiving a loopback feedback signal from the memory module; and
a control module configured to:
transmit the plurality of instruction signals to the memory module via the command and address bus,
receive the loopback feedback signal from the memory module, wherein the loopback feedback signal comprises a looped-back composite version of the plurality of instruction signals, and
determine the information related to the time shift for transmitting instructions on the command and address bus based on the loopback feedback signal.

2. The host controller apparatus according to claim 1 , wherein the control module is configured to determine information related to a setup and/or hold time of the plurality of instruction signals based on the loopback feedback signal, and to determine the information related to the time shift for transmitting instructions on the command and address bus based on the information related to the setup and/or hold time of the plurality of instruction signals.

3. The host controller apparatus according to claim 1 , wherein the loopback feedback signal comprises a looped-back XOR-ed version of the plurality of instruction signals.

4. The host controller apparatus according to claim 1 , wherein the control module is configured to sample the loopback feedback signal received via the interface asynchronously.

5. The host controller apparatus according to claim 1 , wherein the control module is configured to transmit a sequence of signal state vectors within the plurality of instruction signals, wherein the loopback feedback signal comprises a looped-back composite version for each signal state vector of the sequence of signal state vectors.

6. The host controller apparatus according to claim 5 , wherein the control module is configured to determine the sequence of signal state vectors by choosing a signal state vector from a first plurality of signal state vectors in a first transmission state and by choosing a signal state vector from a second plurality of signal state vectors in a second transmission state, and wherein the control module is configured to alternate between the first transmission state and the second transmission state based on a pre-defined transmission schedule.

7. The host controller apparatus according to claim 6 , wherein the pre-defined transmission schedule specifies, that the first transmission state lasts a single clock cycle, and that the second transmission state lasts at least three clock cycles.

8. The host controller apparatus according to claim 6 , wherein an instruction signal of the plurality of instruction signals is related to a chip select instruction of the memory module, wherein at least a subset of signal state vectors of the first plurality of signal state vectors assert the instruction signal of the plurality of instruction signals related to the chip select instruction.

9. The host controller apparatus according to claim 6 , wherein the control module is configured to obtain signal vectors of the first plurality of signal vectors and signal vectors of the second plurality of signal vectors from at least one buffer structure.

10. The host controller apparatus according to claim 5 , wherein the control module is configured to compare the looped-back composite version for each signal state vector of the sequence of signal state vectors to an expected result for each signal state vector of the sequence of signal state vectors, wherein the control module is configured to determine the information related to the time shift for transmitting instructions on the command and address bus based on the comparison of the looped-back composite version for each signal state vector of the sequence of signal state vectors and the expected result for each signal state vector of the sequence of signal state vectors.

11. The host controller apparatus according to claim 10 , wherein the control module is configured to count the number of successful comparisons or the number of unsuccessful comparisons to determine the information related to the time shift for transmitting instructions on the command and address bus.

12. The host controller apparatus according to claim 1 , wherein the control module is configured to control a time shift of instructions transmitted via the command and address bus relative to a clock signal based on the information related to the time shift for transmitting instructions on the command and address bus.

13. The host controller apparatus according to claim 12 , wherein the command and address bus comprises a plurality of signal lines, wherein the control module is configured to control the time shift of instructions transmitted via the command and address bus relative to a clock signal individually for the plurality of signal lines.

14. The host controller apparatus according to claim 1 , wherein the command and address bus comprises a plurality of signal lines, wherein the control module is configured to determine the information related to the time shift for transmitting instructions on the command and address bus individually for the plurality of signal lines.

15. The host controller apparatus according to claim 1 , wherein the control module is configured to transmit the plurality of instruction signals to the memory module using a double-pumped signal transmission.

16. The host controller apparatus according to claim 1 , wherein the memory module is a dual in-line memory module.

17. The host controller apparatus according to claim 1 , wherein the interface is configured to transmit the plurality of instruction signals to one or more dynamic random access memory modules of the memory module and to receive the loopback feedback signal from the one or more dynamic random access memory modules of the memory module.

18. The host controller apparatus according to claim 1 , wherein the interface is configured to transmit the plurality of instruction signals to a registering clock driver of the memory module and to receive the loopback feedback signal from the registering clock driver of the memory module.

19. A host controller for a memory module, the host controller comprising the host controller apparatus according to claim 1 .

20. A method for determining information related to a time shift for transmitting instructions on a command and address bus, the method comprising
transmitting a plurality of instruction signals to the memory module via the command and address bus,
receiving a loopback feedback signal from the memory module, wherein the loopback feedback signal comprises a looped-back composite version of the plurality of instruction signals, and
determining the information related to the time shift for transmitting instructions on the command and address bus based on the loopback feedback signal.

Assignees

• Intel Corp

Inventors

• Jue Christina
• Morris Tonia
• Wu Zhenglong
• Ellis David
• Becerra Daniel

Classifications

• G06F13/4234

  being a memory bus · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title