Memory controller assisted address mapping

Patent metadata

Field	Value
Publication number	US-10635599-B2
Application number	US-201816046287-A
Country	US
Kind code	B2
Filing date	Jul 26, 2018
Priority date	Jul 26, 2018
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

An apparatus includes a storage controller, a non-volatile memory die comprising a set of memory elements and a memory die controller associated with the non-volatile memory die. The memory die controller is configured to identify a portion of the non-volatile memory die for mapping logical addresses, read a header of a sub-portion of the identified portion, for a logical address, map a physical address corresponding to the logical address of the sub-portion to a physical-to-logical mapping and transmit the physical-to-logical mapping to the storage controller.

First claim

What is claimed is:

1. An apparatus comprising:
a non-volatile memory die; and
a memory die controller associated with the non-volatile memory die and in response to a mapping request from a storage controller configured to:
read a logical address from a header of a sub-portion of memory;
map a physical address corresponding to the logical address of the sub-portion within a physical-to-logical mapping;
correct data errors in the physical-to-logical mapping; and
transmit the physical-to-logical mapping to the storage controller.

2. The apparatus of claim 1 , wherein:
the storage controller is configured to send the mapping request to the memory die controller, the mapping request configured to return the physical-to-logical mapping.

3. The apparatus of claim 1 , wherein the mapping request identifies a physical address of a block of memory and a number of sub-pages to map in the block of memory.

4. The apparatus of claim 1 , wherein the storage controller is further configured to:
determine that a logical address in the physical-to-logical mapping is corrupted;
retrieve error correction information corresponding to the corrupted logical address; and
generate a corrected value of the determined corrupted logical address, using the error correction information.

5. An apparatus comprising:
a storage controller coupled to a host;
a non-volatile memory die; and
a memory die controller coupled to the storage controller and associated with the non-volatile memory die, configured to:
receive a mapping request from the host;
extract identification information from the mapping request to identify a portion of the non-volatile memory die for mapping logical addresses;
generate physical-to-logical addressing information corresponding to the portion of the non-volatile memory; and
transmit the physical-to-logical addressing information to the host.

6. The apparatus of claim 5 , wherein:
the memory die controller is further configured to:
receive the mapping request from the storage controller; and
transmit the physical-to-logical addressing information to the storage controller for transmission to the host.

7. An apparatus comprising:
a storage device controller;
a plurality of non-volatile memory die; and
a plurality of memory die controllers, each respective memory die controller coupled to a respective non-volatile memory die and the storage device controller and comprising:
request communication circuitry configured to receive a mapping request from the storage device controller identifying a portion and a number of sub-portions of the respective non-volatile memory die for mapping logical addresses;
an address decoder configured to decode information in a header of each sub-portion of the identified portion to retrieve a logical address;
addressing information generation circuitry configured to generate addressing information from the logical address of each sub-portion; and
addressing communication circuitry configured to send addressing information of the identified portion to the storage device controller.

8. The apparatus of claim 7 , wherein each sub-portion includes a respective header comprising a respective logical address and a corresponding body comprising error correction information of the respective logical address.

9. The apparatus of claim 7 , wherein the storage device controller comprises map maintenance circuitry configured to relate each logical address in the addressing information with a physical address of a sub-portion to form a physical-to-logical map of the portion.

10. An apparatus comprising:
a storage device controller;
a plurality of non-volatile memory die; and
a plurality of memory die controllers, each respective memory die controller coupled to a respective non-volatile memory die and the storage device controller and comprising:
request communication circuitry configured to receive an addressing request originating from a host;
a memory parser configured to parse each sub-portion of a portion of memory on a sequential basis, for a logical address;
mapping generation circuitry configured to generate physical-to-logical mapping information from the logical address of each sub-portion; and
addressing communication circuitry configured to send addressing information of the portion of memory to the host.

11. The apparatus of claim 10 , wherein the addressing request is generated by the storage device controller in response to receiving a host command at the storage device controller from the host.

12. The apparatus of claim 10 , wherein the addressing request is generated by the host, and each respective memory die controller is further configured to receive the addressing request from the storage device controller.

13. An apparatus comprising:
a storage controller;
a plurality of non-volatile memory die;
a plurality of non-volatile memory controllers associated with the plurality of non-volatile memory die, each non-volatile memory controller comprising:
means for reading a respective sub-portion of a portion of a respective non-volatile memory die;
means for retrieving a logical address stored in the respective sub-portion, identified by a respective physical address;
means for determining if the logical address has one or more errors; and
means for storing the logical address with the respective physical address in a physical-to-logical table, in accordance with a determination that the logical address does not have one or more errors.

14. The apparatus of claim 13 , wherein each non-volatile memory controller further comprises:
means for identifying an erroneous value of the logical address in the physical-to-logical table, in accordance with a determination that the logical address has one or more errors.

15. The apparatus of claim 13 , wherein the storage controller further comprises:
means for determining validity of each respective physical address stored in the physical-to-logical table; and
means for creating a validity map of valid physical addresses of the portion.

16. The apparatus of claim 15 , wherein the storage controller further comprises:
means for performing garbage collection operations on the portion of the non-volatile memory die using the validity map.

17. A method comprising:
receiving a control command at a memory die controller of a storage device from a storage controller of the storage device, wherein the control command includes a request to extract a physical-to-logical mapping of a portion of a non-volatile memory die corresponding to the memory die controller;
generating a physical-to-logical mapping for the portion of the non-volatile memory die indexed by physical addresses of the portion, including reading a respective header of each respective sub-portion of the portion, each sub-portion identified by a respective physical address; and
sending the generated physical-to-logical mapping to the storage controller.

18. The method of claim 17 , wherein generating the physical-to-logical mapping includes:
detecting a first logical address at a first physical address of the portion of the non-volatile memory die;
extracting the first logical address from a header of the first physical address; and
determining if the first logical address has one or more errors.

19. The method of claim 18 , further comprising:
in accordance with a determination that the first logical address has one or more errors:
extracting error detection information corresponding to the first logical address stored at the first

Assignees

• Sandisk Technologies Llc

Inventors

• Duzly Yacov
• Li Yan
• Alrod Idan

Classifications

• G06F2212/657

  Virtual address space management · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title