Dynamic reconfiguration of multi-core processor

Patent metadata

Field	Value
Publication number	US-10635453-B2
Application number	US-201816203819-A
Country	US
Kind code	B2
Filing date	Nov 29, 2018
Priority date	Aug 28, 2013
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance.

First claim

The invention claimed is:

1. A microprocessor, comprising a plurality of processing cores and a control unit having a plurality of registers, including a core sync register and a configuration register, which are used to control sleep states of the plurality of processing cores, wherein a disable instruction targeting any enabled one of the plurality of processing cores causes each of the non-targeted cores to:
get interrupted and receive reconfiguration information sent by the targeted core, go into a first sleep state, and stay in the first sleep state until the other cores go into the first sleep state;
wake up after the other cores have gone into the first sleep state, go into a second sleep state, and stay in the second sleep state until the other cores go into the second sleep state; and
wake up after the other cores have gone into the second sleep state and read the configuration register, updated by the targeted core, to determine which of the plurality of processing cores is enabled or disabled;
wherein the control unit outputs clock signals and power signals to each of the processor cores and the control unit controls the sleep state of the processing cores by selectively turning on or off the respective clock signals, wherein the control unit further controls the core power to each of the processing cores by selectively turning on or off the core power signals, and wherein a value in the core sync register is used by the control unit to control the sleep states of the respective processing cores.

2. The microprocessor of claim 1 , wherein the configuration register is configured to indicate whether each of the processing cores is enabled or disabled;
wherein each enabled one of the plurality of processing cores is configured to:
read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled; and
generate a respective configuration-related value based on the read of the configuration register in the first instance;
wherein the configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled; and
wherein each enabled one of the plurality of processing cores is configured to:
read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled; and
generate the respective configuration-related value based on the read of the configuration register in the second instance.

3. The microprocessor of claim 2 , wherein the respective configuration-related value comprises an indicator that indicates whether the processing core is a bootstrap processor of the microprocessor.

4. The microprocessor of claim 2 , wherein the respective configuration-related value comprises a peripheral interrupt controller identifier associated with the processing core.

5. The microprocessor of claim 2 , wherein the configuration register is updated to indicate that the previously enabled one of the plurality of processing cores is disabled in response to the previously enabled processing core writing to a control register.

6. The microprocessor of claim 5 , wherein the previously enabled processing core writes to the control register in response to executing an architectural instruction that instructs the previously enabled processing core to disable itself.

7. The microprocessor of claim 2 , wherein each enabled one of the plurality of processing cores reads the configuration register in the first instance in response to a reset of the microprocessor.

8. The microprocessor of claim 2 , wherein after the update of the configuration register, each enabled one of the plurality of processing cores performs the read of the configuration register in the second instance in response to the previously enabled processing core sending an interrupt request to each of the enabled one of the plurality of processing cores.

9. The microprocessor of claim 1 wherein the control unit is configured to wake up simultaneously each of the plurality of processing cores indicated by the configuration register as enabled in response to determining that each of the plurality of processing cores indicated by the configuration register as enabled has made a respective synchronization request and responsively been put to sleep.

10. The microprocessor of claim 9 , wherein after the configuration register is updated to indicate that the previously enabled one of the plurality of processing cores is disabled, the control unit determines that each of the plurality of processing cores indicated by the configuration register as enabled has made a respective synchronization request and responsively been put to sleep.

11. The microprocessor of claim 1 , wherein the microprocessor comprises a plurality of semiconductor dies;
wherein a distinct subset of the plurality of processing cores is located on each of the plurality of semiconductor dies;
wherein the microprocessor includes an instance of the configuration register on each of the plurality of semiconductor dies; and
wherein each enabled one of the distinct subset of the plurality of processing cores located on each of the plurality of semiconductor dies is configured to read the instance of the configuration register on the semiconductor die.

12. The microprocessor of claim 11 , wherein each instance of the configuration register is updated to indicate that the previously enabled one of the plurality of processing cores is disabled.

13. The microprocessor of claim 12 , wherein the microprocessor includes an instance of the control unit on each of the plurality of semiconductor dies;
wherein each instance of the control unit is configured to determine that each of the plurality of processing cores indicated by the configuration register as enabled has made a respective synchronization request and responsively been put to sleep; and
wherein for each semiconductor die of the plurality of semiconductor dies, the instance of the control unit is configured to wake up simultaneously each enabled one of the distinct subset of the plurality of processing cores located on the semiconductor die indicated by the configuration register as enabled, in response to determining that each of the plurality of processing cores indicated by the configuration register as enabled has made a respective synchronization request and responsively been put to sleep.

14. A method for re-configuring a multi-core microprocessor having a plurality of processing cores and a control unit having a plurality of registers, including a core sync register and a configuration register, which are used to control sleep states of the plurality of processing cores, each processing core configured to receive a disable instruction, the method comprising the disable instruction targeting any enabled one of the plurality of processing cores causes each of the non-targeted cores:
getting interrupted and receiving reconfiguration information sent by the targeted core, going into a first sleep state, and staying in the first sleep state until the other cores go into the first sleep state;
waking up after the other cores have gone into the first sleep state, going into a second sleep state, and staying in the second sleep state until the other cores go into the second sleep state; and
waking up after the other cores have gone into the second sleep state and reading the configuration register, updated by the targeted core, to determine which of the plurality of processing cores is enabled or disabled;
wherein the control unit outputs clock signals and power signals to each of the processor co

Assignees

• Via Tech Inc

Inventors

• Henry G Glenn
• Parks Terry
• Gaskins Darius D

Classifications

• G06F2212/62

  Details of cache specific to multiprocessor cache arrangements · CPC title

• G06F13/42

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title

• G06F12/084

  with a shared cache · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title