Data transfer techniques for multiple devices on a shared bus

Patent metadata

Field	Value
Publication number	US-10635342-B2
Application number	US-201816184307-A
Country	US
Kind code	B2
Filing date	Nov 8, 2018
Priority date	Oct 30, 2015
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

Direct data transfer between devices having a shared bus may be implemented with reduced involvement from a controller associated with the devices. A controller, a source memory device, and a target memory device may be coupled with a shared bus. The controller may identify a source address at the source memory device for data to be transferred to the target memory device. The controller also may identify a target address in the target memory device, and initiate a data transfer directly from the source to the target through a command that is received at both the source and the target memory device. In response to the command, the source memory device may read data out to the bus, and the target memory may read the data from the bus and store the data starting at the target address without further commands from the controller.

First claim

What is claimed is:

1. A method of operating a memory system, comprising:
identifying, at a memory controller, an address in a source memory for data to be transferred to a target memory;
sending, by the memory controller, a single command sequence to the target memory and the source memory based at least in part on identifying the address, wherein the single command sequence indicates a first operation at the source memory and a second operation at the target memory; and
transferring the data from the address in the source memory to the target memory based at least in part on the single command sequence.

2. The method of claim 1 , wherein sending the single command sequence further comprises:
providing a chip enable signal to the source memory and the target memory.

3. The method of claim 2 , wherein sending the single command sequence further comprises:
providing a clock to the source memory and the target memory for a time duration.

4. The method of claim 3 , further comprising:
decoding the single command sequence at the source memory and the target memory based at least in part on the chip enable signal and the clock.

5. The method of claim 3 , wherein the time duration corresponds to an amount of data to be transferred to the target memory.

6. The method of claim 1 , wherein the single command sequence is received at both the source memory and the target memory.

7. The method of claim 6 , wherein the first operation comprises a read operation at the source memory and the second operation comprises a write operation at the target memory.

8. The method of claim 7 , wherein the read operation and the write operation occur concurrently.

9. The method of claim 1 , wherein the single command sequence comprises a target address in the target memory, wherein the target address stores the data transferred from a source address in the source memory.

10. The method of claim 1 , wherein the memory controller, the source memory and the target memory are each coupled with a bus.

11. A method of operating a memory system, comprising:
setting an address in a target memory for storing data received at the target memory; and
sending a single command sequence to both a source memory and the target memory to store the data from the source memory at the target memory based at least in part on setting the address in the target memory, wherein the single command sequence indicates a first operation at the source memory and a second operation at the target memory.

12. The method of claim 11 , wherein the single command sequence comprises an indication to read data out of the source memory to a bus, wherein the bus is coupled with the target memory and the source memory.

13. The method of claim 11 , wherein the single command sequence is received at both the source memory and the target memory.

14. The method of claim 11 , wherein the first operation comprises a read operation at the source memory and the second operation comprises a write operation at the target memory.

15. The method of claim 14 , wherein the read operation and the write operation occur at a same time.

16. An apparatus for data transfer, comprising:
a source memory coupled with a bus;
a target memory coupled with the bus; and
a controller coupled with the bus and in electronic communication with the source memory and the target memory, wherein the controller is operable to:
identify an address in the source memory for data to be transferred to the target memory;
send a single command sequence to the target memory and the source memory based at least in part on identifying the address, wherein the single command sequence indicates a first operation at the source memory and a second operation at the target memory; and
transfer the data from the address in the source memory to the target memory based at least in part on the single command sequence.

17. The apparatus of claim 16 , wherein the controller is further operable to:
provide a chip enable signal to the source memory and the target memory; and
provide a clock to the source memory and the target memory for a time duration, wherein the time duration corresponds to an amount of data to be transferred to the target memory.

18. The apparatus of claim 17 , wherein the controller is further operable to:
provide an instruction to decode the single command sequence at the source memory and the target memory based at least in part on the chip enable signal and the clock.

19. The apparatus of claim 16 , wherein the single command sequence is received at both the source memory and the target memory.

20. The apparatus of claim 16 , wherein the first operation comprises a read operation at the source memory and the second operation comprises a write operation at the target memory, wherein the read operation and the write operation occur concurrently.

Assignees

• Micron Technology Inc

Inventors

• Zhang Yihua
• Cooke James

Classifications

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F3/061

  Improving I/O performance · CPC title