Data availability during memory inaccessibility

Patent metadata

Field	Value
Publication number	US-10635327-B2
Application number	US-201815885770-A
Country	US
Kind code	B2
Filing date	Jan 31, 2018
Priority date	Jan 31, 2018
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

Apparatuses, systems, and methods are disclosed for data availability during temporary inaccessibility of a memory region for memory. An apparatus may include a plurality of memory elements and a controller. A controller may be configured to identify a portion of memory of a plurality of memory elements such that data stored in a portion of memory is temporarily inaccessible and other data stored in other portions of memory in the plurality of memory elements is accessible. A controller may be configured to reconstruct data stored in a portion of memory from other data stored in other portions of memory. A controller may be configured to provide reconstructed data while a portion of an array is temporarily inaccessible.

First claim

What is claimed is:

1. An apparatus comprising:
a plurality of memory elements; and
a controller configured to:
initiate a refresh activity for a first portion of memory of the plurality of memory elements, wherein the refresh activity for the first portion of memory comprises refreshing data of the first portion of memory by re-writing the data to the first portion of memory;
prevent refresh activity for a second portion of memory and a data reconstruction portion of memory during the refresh activity for the first portion of memory, wherein the second portion of memory stores data other than the data of the first portion of memory, and the data reconstruction portion stores parity data usable with the data stored in the second portion of memory to reconstruct the data stored in the first portion of memory;
in response to a read request received during the refresh activity for the first portion of memory, reconstruct the data stored in the first portion of memory from the parity data and the data stored in the second portion of memory; and
provide the reconstructed data.

2. The apparatus of claim 1 , wherein the first portion of memory comprises a memory element of the plurality of memory elements.

3. The apparatus of claim 1 , wherein error correction information is distributed among the plurality of memory elements, and the controller uses the error correction information to correct memory of individual elements in the plurality of memory elements before reconstructing the data stored in the first portion of memory.

4. The apparatus of claim 1 , wherein error correction information is stored in one or more elements in the plurality of memory elements separate from elements storing user data in the plurality of memory elements, and the controller uses the error correction information to correct the data of the first portion of memory after reconstructing the data stored in the first portion of memory.

5. The apparatus of claim 1 , wherein the controller pauses the refresh activity for the first portion of memory in response to a write request to the first portion of memory.

6. The apparatus of claim 1 , wherein the controller buffers write requests to the first portion of memory and applies the write requests after completion of the refresh activity for the first portion of memory.

7. The apparatus of claim 1 , wherein the controller waits for received writes to finish before initiating the refresh activity for the first portion of memory.

8. A method comprising:
initiating a refresh activity for a first portion of memory of a plurality of memory elements, wherein the refresh activity for the first portion of memory comprises refreshing data of the first portion of memory by re-writing the data to the first portion of memory;
preventing refresh activity for a second portion of memory and a data reconstruction portion of memory during the refresh activity for the first portion of memory, wherein the second portion of memory stores data other than the data of the first portion of memory, and the data reconstruction portion stores parity data usable with the data stored in the second portion of memory to reconstruct data stored in the first portion of memory;
in response to a read request received during the refresh activity for the first portion of memory, reconstructing data from the first portion of memory based on the parity data and the data stored in the second portion of memory; and
providing the reconstructed data.

9. The method of claim 8 , wherein reconstructing the data from the first portion of memory comprises:
using error correction information to correct memory of the second portion of memory; and
reconstructing the data on the first portion of memory using the parity data and the data stored in the second portion of memory.

10. The method of claim 9 , further comprising using the error correction information to correct the reconstructed data after reconstructing the data on the first portion of memory.

11. The method of claim 8 , further comprising:
receiving a write request to the first portion of memory;
pausing the refresh activity for the first portion of memory; and
writing to the first portion of memory.

12. The method of claim 8 , further comprising:
receiving a write request to the first portion of memory;
buffering the write request; and
applying the write request after completion of the refresh activity for the first portion of memory.

13. An apparatus comprising:
means for initiating a refresh activity for a first portion of memory of a plurality of memory elements, wherein the refresh activity for the first portion of memory comprises refreshing data of the first portion of memory by re-writing the data to the first portion of memory;
means for preventing refresh activity a second portion of memory and a data reconstruction portion of memory during the refresh activity for the first portion of memory, wherein the second portion of memory stores data other than the data of the first portion of memory, and the data reconstruction portion stores parity data usable with the data stored in the second portion of memory to reconstruct data stored in the first portion of memory;
means for reconstructing data of the first portion of memory in response to a read request received during the refresh activity for the first portion of memory, by correcting errors in the second portion of memory and reconstructing the data of the first portion of memory based on the parity data and the data stored in the second portion of memory; and
means for providing the reconstructed data in response to the read request.

14. The apparatus of claim 13 , further comprising means for handling write requests to the first portion of memory.

15. The apparatus of claim 14 , wherein the means for handling write requests to the first portion of memory pauses the refresh activity for the first portion of memory while writing to the first portion of memory.

16. The apparatus of claim 13 , further comprising means for correcting errors in the plurality of memory elements.

Assignees

• Western Digital Tech Inc

Inventors

• Helmick Daniel
• Zhang Yuheng
• Ghaly Mai
• Yin Yibo
• Su Hao
• Anderson Kent

Classifications

• G06F11/108 Primary

  Parity data distribution in semiconductor storages, e.g. in SSD · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0665

  at area level, e.g. provisioning of virtual or logical volumes · CPC title

• G06F11/1076

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• G06F11/1012

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title