Integrator for a storage device, corresponding storage device and method of manufacturing the same

US10635320B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10635320-B2
Application numberUS-201816171958-A
CountryUS
Kind codeB2
Filing dateOct 26, 2018
Priority dateOct 27, 2017
Publication dateApr 28, 2020
Grant dateApr 28, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure relates to an integrator for a storage device, a corresponding storage device and a method of manufacturing the same. The integrator comprises a base board comprising a first interface and a second interface; a connector coupled to the first interface of the base board, the connector being connectable with at least one server in the storage device; an input/output (I/O) part coupled to the second interface of the base board and connectable with an I/O device; and a switcher arranged on the base board and adapted to exchange data between the first interface and the second interface to support data transmission of the I/O device or other servers with the server via the integrator.

First claim

Opening claim text (preview).

We claim: 1. An integrator for a storage device, comprising: a base board comprising a first interface and a second interface; one or more connectors coupled to the first interface of the base board, the one or more connectors being connectable with a set of multiple servers in the storage device; one or more input/output (I/O) parts coupled to the second interface of the base board and connectable with first and second I/O devices of different types; and a switcher arranged on the base board and adapted to exchange data between the first and second interfaces to support data transmission of the first and second I/O devices with the set of multiple servers via the integrator; wherein the integrator is deployed in a separate integrator chassis relative to the set of multiple servers and the first and second I/O devices, the set of multiple servers and the first and second I/O devices thereby being deployed external to the integrator chassis. 2. The integrator of claim 1 , wherein the one or more connectors are compliant with Peripheral Component Interconnect Express (PCIe) protocol. 3. The integrator of claim 2 , wherein the one or more input/output (I/O) parts are compliant with at least one of the following protocols: PCIe protocol, Ethernet protocol, Serial SCSI (SAS) protocol, Fiber Channel (FC) protocol, Infiniband (IB) protocol, small input/output card (SLIC) protocol and non-volatile memory express (NVME) protocol. 4. The integrator of claim 1 , wherein the switcher comprises a plurality of PCIe switch chips. 5. The integrator of claim 4 , wherein the data is exchanged between the PCIe switch chips via a non-transparent bridge (NTB). 6. The integrator of claim 1 , further comprising a heat radiator ( 107 ) for dissipating heat for the integrator. 7. The integrator of claim 1 , further comprising a power supply module coupled to the base board for powering the integrator. 8. A storage device, comprising: a set of multiple servers; first and second I/O devices of different types; and an integrator comprising: a base board comprising a first interface and a second interface; one or more connectors coupled to the first interface of the base board, the one or more connectors being connectable with the set of multiple servers in the storage device; one or more input/output (I/O) parts coupled to the second interface of the base board and connectable with the first and second I/O devices; and a switcher arranged on the base board and adapted to exchange data between the first and second interfaces to support data transmission of the first and second I/O devices with the set of multiple servers via the integrator; wherein the integrator is deployed in a separate integrator chassis relative to the set of multiple servers and the first and second I/O devices, the set of multiple servers and the first and second I/O devices thereby being deployed external to the integrator chassis. 9. A method for manufacturing an integrator for a storage device, comprising: providing a base board comprising a first interface and a second interface; coupling one or more connectors to the first interface of the base board, the one or more connectors being connectable with a set of multiple servers in the storage device; coupling one or more input/output (I/O) parts to the second interface of the base board, the one or more input/output (I/O) parts (being connectable with first and second I/O devices of different types; and arranging a switcher on the base board, the switcher being adapted to exchange data between the first and second interfaces to support data transmission of the first and second I/O devices with the set of multiple servers via the integrator; wherein the integrator is deployed in a separate integrator chassis relative to the set of multiple servers and the first and second I/O devices, the set of multiple servers and the first and second I/O devices thereby being deployed external to the integrator chassis. 10. The integrator of claim 1 , wherein at least one of the first and second I/O devices comprises at least one of a storage array enclosure and a non-volatile memory cluster. 11. The integrator of claim 1 , wherein the one or more connectors comprise one or more removable connectors. 12. The integrator of claim 1 , wherein the one or more connectors are connectable with the set of multiple servers by wire or wirelessly. 13. The integrator of claim 1 , wherein the one or more connectors comprise a plurality of connectors and the one or more input/output (I/O) parts comprise a plurality of input/output (I/O) parts. 14. The storage device of claim 8 , wherein at least one of the first and second I/O devices comprises at least one of a storage array enclosure and a non-volatile memory cluster. 15. The storage device of claim 8 , wherein the one or more connectors comprise one or more removable connectors. 16. The storage device of claim 8 , wherein the one or more connectors are connectable with the set of multiple servers by wire or wirelessly. 17. The storage device of claim 8 , wherein the one or more connectors comprise a plurality of connectors and the one or more input/output (I/O) parts comprise a plurality of input/output (I/O) parts. 18. The method of claim 9 , wherein at least one of the first and second I/O devices comprises at least one of a storage array enclosure and a non-volatile memory cluster. 19. The method of claim 9 , wherein the one or more connectors comprise one or more removable connectors. 20. The method of claim 9 , wherein the one or more connectors comprise a plurality of connectors and the one or more input/output (I/O) parts comprise a plurality of input/output (I/O) parts.

Assignees

Inventors

Classifications

  • Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

  • being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

  • Serial attached SCSI [SAS] · CPC title

  • Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

  • by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device · CPC title

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What does patent US10635320B2 cover?
The present disclosure relates to an integrator for a storage device, a corresponding storage device and a method of manufacturing the same. The integrator comprises a base board comprising a first interface and a second interface; a connector coupled to the first interface of the base board, the connector being connectable with at least one server in the storage device; an input/output (I/O) p…
Who is the assignee on this patent?
Emc Ip Holding Co Llc
What technology area does this patent fall under?
Primary CPC classification G06F3/061. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Apr 28 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).