Signal processing circuit for electrostatic capacity type touch sensor

Patent metadata

Field	Value
Publication number	US-10635220-B2
Application number	US-79685010-A
Country	US
Kind code	B2
Filing date	Jun 9, 2010
Priority date	Jun 10, 2009
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

There is offered a signal processing circuit for an electrostatic capacity type touch sensor which can improve the noise tolerance and adjust an offset in the output voltage. The signal processing circuit for the touch sensor is structured to include an alternating current power supply providing an excitation pad with an alternating voltage, an electric charge amplifier generating an output voltage Vout corresponding to a difference between a capacitance of a first capacitor formed between a first touch pad and the excitation pad and a capacitance of a second capacitor formed between a second touch pad and the excitation pad, and an offset adjustment circuit to adjust an offset in the output voltage Vout of the electric charge amplifier.

First claim

What is claimed is:

1. A signal processing circuit for an electrostatic capacity touch sensor wherein the signal processing circuit receives a signal from a first touch pad and a second touch pad disposed on a touch panel having an excitation pad disposed between the first touch pad and the second touch pad, the touch panel including a substrate, the touch panel also including the first touch pad disposed on the substrate, the second touch pad disposed on the substrate, and the excitation pad disposed on the substrate, the excitation pad being disposed between the first touch pad and the second touch pad;
the signal processing circuit comprising:
a first alternating current power supply configured to generate a first alternating voltage, and apply the first alternating voltage to the excitation pad;
an electric charge amplifier configured to generate an output voltage corresponding to a difference between a first capacitance of a first capacitor and a second capacitance of a second capacitor when the first alternating voltage is applied to the excitation pad, the first capacitor being formed between the first touch pad and the excitation pad, and the second capacitor being formed between the second touch pad and the excitation pad, the electronic charge amplifier having a first input configured for connecting to the first capacitor and a second input configured for connecting to the second capacitor, the electronic charge amplifier also including a first output and a second output;
a first feedback capacitor connected between the first output of the electronic charge amplifier and the first input of the electronic charge amplifier;
a first feedback switch connected between the first output of the electronic charge amplifier and the first input of the electronic charge amplifier, and connected in parallel to the first feedback capacitor;
a second feedback capacitor connected between the second output of the electronic charge amplifier and the second input of the electronic charge amplifier;
a second feedback switch connected between the second output of the electronic charge amplifier and the second input of the electronic charge amplifier, and connected in parallel to the second feedback capacitor;
a third capacitor connected in series with the first capacitor, the third capacitor having a first variable capacitance, the third capacitor configured for connecting to the first input of the electronic charge amplifier;
a fourth capacitor connected in series with the second capacitor, the fourth capacitor having a second variable capacitance, the fourth capacitor configured for connecting to the second input of the electronic charge amplifier;
a second alternating current power supply configured to generate a second alternating voltage that is opposite in phase to the first alternating voltage and to apply the second alternating voltage to the third capacitor and the fourth capacitor, the second alternating current power supply coupled to the first capacitor through the third capacitor and coupled to the second capacitor through the fourth capacitor, the third capacitor and the fourth capacitor configured for connecting between the second alternating current power supply and respective first and second inputs of the electronic charge amplifier; and
an offset adjustment circuit configured to adjust the first variable capacitance and the second variable capacitance to adjust an offset in the output voltage of the electric charge amplifier so that a difference between the first variable capacitance and the second variable capacitance is equal to the difference between the first capacitance of the first capacitor and the second capacitance of the second capacitor.

2. The signal processing circuit of claim 1 , wherein the offset adjustment circuit adjusts the first variable capacitance of the third capacitor or the second variable capacitance of the fourth capacitor in response to the output voltage of the electric charge amplifier when the second alternating voltage is applied to the third capacitor or the fourth capacitor.

3. The signal processing circuit of claim 2 , wherein the third capacitor comprises:
a plurality of first adjustment capacitors, and
a first switching circuit configured to connect one of the plurality of first adjustment capacitors selected by a first adjustment signal from the offset adjustment circuit so that the selected one of the plurality of first adjustment capacitors connects the first capacitor and the second alternating current power supply, and
the fourth capacitor comprises:
a plurality of second adjustment capacitors, and
a second switching circuit configured to connect one of the plurality of second adjustment capacitors selected by a second adjustment signal from the offset adjustment circuit so that the selected one of the plurality of second adjustment capacitors connects the second capacitor and the second alternating current power supply.

4. The signal processing circuit of claim 3 , further comprising an electrically writable/erasable non-volatile memory, and a control circuit configured to write the first adjustment signal and the second adjustment signal from the offset adjustment circuit into the non-volatile memory.

5. The signal processing circuit of claim 4 , wherein the control circuit is configured to read the first adjustment signal and the second adjustment signal out of the non-volatile memory and set the first adjustment signal and the second adjustment signal into the offset adjustment circuit.

6. The signal processing circuit of claim 1 , wherein the second alternating current power supply includes a first terminal coupled to a first terminal of the third capacitor and to a first terminal of the fourth capacitor.

7. The signal processing circuit of claim 1 , wherein the first alternating current power supply is connected to a first terminal of the first capacitor and to a first terminal of the second capacitor;
a second terminal of the first capacitor is connected to a first terminal of the third capacitor, and a second terminal of the third capacitor is connected to the second alternating current power supply; and
a second terminal of the second capacitor is connected to a first terminal of the fourth capacitor, and a second terminal of the fourth capacitor is connected to the second alternating current power supply.

8. The signal processing circuit of claim 1 , wherein the second alternating current power supply has a first terminal connected to a ground reference voltage and a second terminal connected to both the third capacitor and the fourth capacitor.

9. The signal processing circuit of claim 1 wherein the signal processing circuit is configured to close the first feedback switch and the second feedback switch in a first mode.

10. The signal processing circuit of claim 9 wherein the signal processing circuit is configured to open the first feedback switch and the second feedback switch in a second mode different from the first mode.

11. The signal processing circuit of claim 10 wherein the signal processing circuit is configured to alternate between the first mode and the second mode a multitude of times.

12. The signal processing circuit of claim 1 wherein the first feedback capacitor includes a first terminal and a second terminal, the first terminal connected to the first output of the electric charge amplifier and the second terminal connected to the first input of the electric charge amplifier.

13. The signal processing circuit of claim 12 wherein the second feedback capacitor includes a third terminal and a fourth terminal, the third terminal connected to the second output of the elect

Assignees

• Kobayashi Kazuyuki
• Suzuki Tatsuya
• Fukai Kumiko
• Kaneta Yasuhiro
• Semiconductor Components Ind Llc

Inventors

• Kobayashi Kazuyuki
• Suzuki Tatsuya
• Fukai Kumiko
• Kaneta Yasuhiro

Classifications

• G06F3/0443

  using a single layer of sensing electrodes · CPC title

• G06F3/044

  by capacitive means · CPC title

• G06F3/0418

  for error correction or compensation, e.g. based on parallax, calibration or alignment · CPC title

• G06F3/0416 Primary

  Control or interface arrangements specially adapted for digitisers · CPC title

• G06F3/04164

  Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads · CPC title