Reference voltage circuit and semiconductor device
US-2018348807-A1 · Dec 6, 2018 · US
Constant current circuit, semiconductor device, electronic apparatus, and method of manufacturing semiconductor device
US10635126B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10635126-B2 |
| Application number | US-201916365767-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 27, 2019 |
| Priority date | Mar 28, 2018 |
| Publication date | Apr 28, 2020 |
| Grant date | Apr 28, 2020 |
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- Title
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Abstract
Official abstract text for this publication.
In an N-channel depletion type first transistor, a gate is connected to a reference node and a drain is connected to a current output node. In a P-channel enhancement type second transistor, a gate and a drain are connected to the reference node and a source is connected to a source of the N-channel depletion type first transistor.
First claim
Opening claim text (preview).
What is claimed is: 1. A constant current circuit comprising: a depletion type first transistor in which a first conductivity type is included, a gate is connected to a reference node, and a drain is connected to a current output node; and an enhancement type second transistor in which a second conductivity type reverse to the first conductivity type is included, a gate and a drain are connected to the reference node, and a source is connected to a source of the first transistor. 2. The constant current circuit according to claim 1 , wherein the first conductivity type is N-channel and the second conductivity type is P-channel. 3. A semiconductor device comprising the constant current circuit according to claim 2 . 4. The constant current circuit according to claim 1 , wherein the first conductivity type is P-channel and the second conductivity type is N-channel. 5. A semiconductor device comprising the constant current circuit according to claim 4 . 6. A semiconductor device comprising the constant current circuit according to claim 1 . 7. An electronic apparatus comprising the semiconductor device according to claim 6 . 8. A method of manufacturing a semiconductor device including a constant current circuit that includes a depletion type first transistor in which a first conductivity type is included, a gate is connected to a reference node, and a drain is connected to a current output node, and an enhancement type second transistor in which a second conductivity type reverse to the first conductivity type is included, a gate and a drain are connected to the reference node, and a source is connected to a source of the first transistor, the method comprising: forming a channel dope layer of the first transistor and a channel dope layer of the second transistor in a common production process using a common mask.
Assignees
Inventors
Classifications
- G05F3/24Primary
wherein the transistors are of the field-effect type only (G05F3/205, G05F3/26, G05F3/30 take precedence) · CPC title
Electricity · mapped topic
Electricity · mapped topic
Complementary IGFETs, e.g. CMOS · CPC title
using silicon technology, e.g. SiGe · CPC title
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Frequently asked questions
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- What does patent US10635126B2 cover?
- In an N-channel depletion type first transistor, a gate is connected to a reference node and a drain is connected to a current output node. In a P-channel enhancement type second transistor, a gate and a drain are connected to the reference node and a source is connected to a source of the N-channel depletion type first transistor.
- Who is the assignee on this patent?
- Seiko Epson Corp
- What technology area does this patent fall under?
- Primary CPC classification G05F3/24. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Apr 28 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).