Syndrome of degraded quantum redundancy coded states

Patent metadata

Field	Value
Publication number	US-10633248-B2
Application number	US-201815911909-A
Country	US
Kind code	B2
Filing date	Mar 5, 2018
Priority date	Jan 15, 2013
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

An apparatus includes a device having n input ports and n output ports. The n input ports are configured to receive n corresponding physical objects of a physically processed, quantum redundancy coded state. The n output ports are configured to output the n physical objects in the physically processed, quantum redundancy coded state. The device is configured to measure bits of a syndrome of the physically processed, quantum redundancy coded state by passing the n physical objects through the device. The device is configured to measure a parity check bit for the measured bits of the syndrome by the passing the n physical objects through the device.

First claim

What is claimed is:

1. Apparatus, comprising:
a device having n input ports to receive corresponding n physical objects of a physically processed, quantum redundancy coded state and having n output ports to output the n physical objects in the physically processed, quantum redundancy coded state, the device being configured to measure bits of a syndrome of the physically processed, quantum redundancy coded state by passing the n physical objects through the device; and
wherein the device is configured to measure a parity check bit for some of the measured bits of the syndrome by the passing the n physical objects through the device.

2. The apparatus of claim 1 , wherein the device includes a sequence of serially connected measurement devices, each of the measurement devices being configured to receive and transmit the n physical objects and being configured to measure either one of the bits of the syndrome or the parity check bit for some of the measured bits of the syndrome.

3. The apparatus of claim 2 , wherein at least, one of the measurement devices is configured to measure the parity check bit.

4. The apparatus of claim 2 , wherein each of the measurement devices includes a quantum circuit of quantum gates.

5. The apparatus of claim 2 , wherein a proper subset of the measurement devices are configured to measure the bits of the syndrome such that each bit of the syndrome is measured by a different one of the measurement devices of the proper subset.

6. The apparatus of claim 5 , further comprising a controller being connected to receive the measured bits of the syndrome and the measured parity check bit and being configured to determine an error-corrected value of the syndrome based on the measured parity check bit and the measured bits of the syndrome.

7. The apparatus of claim 6 , wherein the controller is configured to error correct the syndrome measured by the proper subset of the measurement devices according to a linear block code.

8. The apparatus of claim 6 , further comprising an error-correction module being configured to error-correct the physically processed, quantum redundancy coded state based on an error-corrected value of the syndrome produced by the electronic controller.

Assignees

• Alcatel Lucent

Inventors

• Ashikhmin Alexei

Classifications

• B82Y10/00 Primary

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• G06N10/00

  Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title

• H03M13/13 Primary

  Linear codes · CPC title

• G06N10/70

  Quantum error correction, detection or prevention, e.g. surface codes or magic state distillation · CPC title

• G06N10/40

  Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title